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This paper introduces design and implementation of microwave low noise amplifier (LNA) in 130 nm SOI CMOS technology. The LNA operating around 5.8 GHz is design for ISM 5.8GHz applications. In schematic design, the CMOS transistors are stacked for compact size. In layout verification, all inductors are verified by 3D electromagnetic simulator. The fabricated chip has achieved 7.0 gain and 3.1 dB noise...
In this paper we analyzed the IR drop problem in large scale content addressable memory (CAM) and proposed a simple yet efficient gated power transistor technique. Each row of CAM cells is powered by two metal rails, one for the memory element and another one for the comparison transistors and the match lines. The latter rail is powered by a row-based transistor, which presents a physical “gate” to...
A full current-mode sense amplifier is presented. It extensively utilizes the cross-coupled inverters for both local and global sensing stages, hence achieving ultra low-power and ultra high-speed properties simultaneously. Its sensing delay and power consumption are almost independent of the bit- and data-line capacitances. Extensive pre-layout simulation results based on a 1.8 V/0.18 mum CMOS technology...
In this paper, we present a new CMOS circuit design for increasing the threshold voltages (VT) of MOSFETS to reduce power consumption. Using a single voltage source VDD, the proposed circuit generates both the high positive and negative voltages, which are connected to the body nodes of MOSFETs to increase the reverse-bias voltage between the source and body in order to raise VT. Consequentially,...
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