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Reliability of Superjunction (SJ) MOSFET is closely related to its manufacturing process. Experiments are carried out to investigate the electrical characteristics in high temperature of SJ MOSFET produced by deep trench filling technology. Filling holes are confirmed to be responsible for the performance deterioration in high temperature and the mechanism has been analyzed thoroughly.
An efficient approach to engineering the Al2O3/GaN positive interface fixed charges (Qit+) by post-dielectric annealing in nitrogen is demonstrated. The remarkable reduction of interface fixed charges from 1.44×1013 to 3×1012 cm−2 was observed, which leads to a record high threshold voltage (VTH) of +7.6 V obtained in the Al2O3/GaN MOSFETs. The positive interface charges were proposed originating...
An efficient approach to engineering the AhOß/GaN positive interface fixed charges (Qit+) by post-dielectric annealing in nitrogen is demonstrated. The remarkable reduction of Qit+ from 1.44×1013 to 3×1012 cm−2 was observed, which leads to a record high threshold voltage (Vth) of +7.6 V obtained in the AhOß/GaN MOSFETs. The positive interface charges were proposed originating from the N-vacancy and...
Due to the limitation in circuit measurements using current and voltage probes, the conventional ways of measuring switching losses lack the physical insight of the complicated witching process in power devices such as the SiC power MOSFET. This paper seeks to have a better understanding of the dynamic turn-on and turn-off processes of the SiC power MOSFET. Using a detailed finite element simulation...
Wide bandgap semiconductor devices like SiC have achieved more and more attentions in electric vehicles-(EVs) because of their high-temperature capability, high-power density, and high efficiency. As all known, EVs frequently operate in acceleration, deceleration and low speed driving in urban traffic. Thus, not only the rated operation condition should be considered, but also some extreme operation...
An improved breakdown voltage LDMOS with reduced specific on-resistance is proposed and its mechanism is investigated. The LDMOS is characterized by a junction-type field plate (JFP) and an N+ floating layer (NFL) in the p-substrate. First, the linear doped JFP not only modulates the surface electric field (E-field) distribution of the drift region to make it more uniform and thus increases the breakdown...
Sneak circuit in power electronic circuit is a newly discovered phenomenon. Analysis of sneak circuit is essential for power electronics converter because of its unpredictable feature and various influences. Sneak circuit phenomenon is found in the Boost converter which takes parasitic parameters into consideration and the major exciting conditions are discussed in this paper. The effects of sneak...
A superjunction LDMOST with a floating oppositely doped buried layer in p-substrate is proposed. The buried layer provides another pn junction to sustain drain voltage, reduces the substrate-assisted-depletion effect and generates new electric field, which modulates the bulk electric field in off-state. Simulation results show that the proposed structure achieves significant breakdown voltage improvement...
This paper investigates the effect of field plate on a new super junction LDMOS-surface low on-resistance path (SLOP) LDMOS. The surface electric field of SLOP-LDMOS focuses at source and drain end because of the RESURF structure under super junction (SJ). Field plate improves electric field distribution of SLOP-LDMOS by improving the charge balance of SJ, which is different from conventional LDMOS...
A new super junction LDMOS (SJ-LDMOS) on partial silicon-on-insulator (SOI) with composite substrate is presented in this paper. The thin super junction structure on the buried oxide (BOX) provides the surface low on-resistance path, which is attributed to the heavy doping trait of SJ. The N-buffer layer is introduced under the BOX to sustain vertical voltage, which reduces the substrate-assisted...
The SOI LDMOSFETs with step doping profiles in drift region have been experimentally investigated. Uniform, single-step and two-step doped drift regions have been designed and fabricated on a same bonded SOI wafer with the top silicon layer of 3 mum and buried oxide layer of 1.5 mum. The experimental devices with two-step doping profile have a breakdown voltage in access of 250 V and specific on-resistance...
The two structures of over 650V MR & MR SLMFFP double RESURF LDMOSs with HVI are experimentally realized using SPSM BCD process for high side gate drive IC. The experimental results, coincident with the three-dimensional simulations, show that the breakdown voltage of LDMOS will increase by reducing the width of HVI metal line. The breakdown voltages of the MR double RESURF LDMOS are 670V, 760V,...
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