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Multi-level-cell (MLC) is a critical technology to achieve low bit cost for phase change memory. However, resistance drift is an intrinsic material property that kills memory window and imposes formidable challenges for MLC. In this work, we report a radically different sensing concept that exploits the non-linear R-V characteristics of PCM that can easily accommodate 8 resistance levels in three...
In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of a 3 Mega pixel CMOS image sensor is temporary bonded to a silicon carrier wafer with thermal plastic material and ZoneBond technology. Then the CMOS wafer is thinned down to few microns to detect the light from the backside...
In the study, the direct robust active bonding (DRAB) between Si chip and Al heat sink by using of low melting point Sn-Ag-Ti (SAT) active solder is obtained at 250°C in air. The bonding process was done without flux and without the need for pre-metallization of Al heat sink or a protective atmosphere. The bonded joints were studied using SEM and the distribution of elements using energy-dispersive...
In this study, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding is demonstrated. To realize the signal transmission effects in high speed digital signaling via Cu TSV and Cu/Sn micro-joint interconnection, the insertion loss was investigated by simulation analysis with variable TSV pitches, micro-bump diameters and chip thicknesses. Key technologies...
Ta/Ta2O5 RRAMs show self-compliant characteristics in some Ta or Ta2O5 thickness range but Ti/TaOx RRAMs always need current compliance due to totally consumption of SC conduction layer.
The evolution of the microstructure and magnetic properties of FePt films with different thicknesses fabricated by dc magnetron sputtering on TiN intermediate layer were investigated. MFM results showed that the magnetization reversal mechanism changed from Stoner-Wohlfarth rotation to domain wall motion with increasing film thickness. SEM and TEM images revealed that the morphologies of the films...
The memory performances of the HfOX based bipolar resistive memory, including switching speed and memory reliability, are greatly improved in this work. Record high switching speed down to 300 ps is achieved. The cycling test shed a clear light on the wearing behavior of resistance states, and the correlation between over-RESET phenomenon and the worn low resistance state in the devices is discussed...
Motivated by the recent concept of Space-Time Shift Keying (STSK), we propose a novel cooperative STSK scheme, which is capable of achieving a flexible rate-diversity tradeoff, in the context of cooperative space-time transmissions. More specifically, in our cooperative STSK scheme each Relay Node (RN) activates Decode-and-Forward (DF) transmissions, depending on the success or failure of Cyclic Redundancy...
A novel resistive memory with the TiN/Ti/HfOx/TiN stack is proposed and fully integrated with 0.18 μm CMOS technology. The excellent memory performances such as low operation current (down to 25 μA), low operation voltage (<;1.5 V), high ON/OFF resistance ratio (above 100), and fast switching speed (10 ns) have been demonstrated for this ReRAM. Moreover, the device exhibits excellent scalability...
Since 3D-IC becomes popular nowadays, solder micro-bumps plays an important role to develop TSV technology. This study verifies solder micro-bump efficiency via cracking as index. The micro-bump cracking is observed at the interface of intermetallic compound (IMC) layer after Si chip and Si carrier bonding. It was found that P-rich Ni layer will perform weaker and brittle solder joint by means of...
High density three dimensional (3D) interconnects formed by high aspect ratio through silicon vias (TSVs) and fine pitch solder microbumps are presented in this paper. The aspect ratio of the TSV is larger than 10 and filled with Cu without voids; there are electrical nickel and immersion gold (ENIG) pads on top of the TSV as under bump metallurgy (UBM) layer. On the Si chip, Cu/Sn solder microbumps...
Developments of ultra fine pitch and high density solder microbumps for advanced 3D stacking technologies are discussed in this paper. CuSn solder microbumps with 25 ??m in pitch are fabricated at wafer level by electroplating method and the total thicknesses of the platted Cu and Sn are 10 ??m. After plating, the micro bumps on the Si chip are reflowed at 265??C and the variation of bump height measured...
The robustness and dimensions of metal trace is important for electronic packaging applications. For example, materials with good electrical conductivity are essential for reducing IR drops for integrity of electrical signals. Copper metal has good electrical conductivity and hence is the major materials used in electronic packaging. For example in PCB industry, the common methods to form copper trace...
Tin film about one micron thick was electroplated over a silicon wafer pre-coated with a layer of Cr and another layer of Ni by evaporation. A special sample holder was designed to apply compressive stresses in the electroplated tin film. After incubation in a vacuum oven at 160degC for 7 days, huge hillocks about 10-30 mum diameter and 30-150 mum length grew with a density about 7 per square mm....
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