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The globalization of the semiconductor industry has caused many challenges to prevent intellectual property (IP) piracy. Logic encryption is an effective technique for hardware IP protection. Researchers have proposed various logic encryption techniques, which introduce large overheads in delay, power and area. This paper aims to significantly reduce these overheads by proposing a novel gate replacement-based...
Packet-switched Network-on-Chip (NoC) is the shared global communication infrastructure for future large-scale chip multi-processors (CMPs). Recently, Single-cycle Multi-hop Asynchronous Repeated Traversal (SMART) on repeater-inserted wires to reduce packet delay was proposed. But current NoC with SMART support adds complexity to conventional routers and incurs high power consumption. In this paper,...
Third-party intellectual property (3PIP) cores are widely used in integrated circuit designs. It is essential and important to ensure their trustworthiness. Existing hardware trust verification techniques suffer from high computational complexity, low extensibility, and inability to detect implicitly-triggered hardware trojans (HTs). To tackle the above problems, in this paper, we present a novel...
Integrated circuits suffer from severe variation effects with technology scaling, making their timing behavior increasingly unpre-dictable. Timing speculation is a promising technique to tackle this problem with the help of online timing error detection and correction mechanisms. In this paper, we propose to use redundancy addition and removal (RAR) technique to optimize timing-speculated circuits...
Power distribution network (PDN) designs for today's high performance integrated circuits (ICs) typically occupy a significant share of metal resources in the circuit, and hence defects may be introduced on PDNs during the manufacturing process. Since we cannot afford to over-design the PDNs to tolerate all possible defects, it is necessary to conduct manufacturing test for them. In this paper, we...
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. In contrast to prior work, we consider the pre-bond test-pin-count constraint during optimization since these pins occupy large silicon area that cannot be used in functional mode. In addition, the proposed test-architecture...
Post-silicon validation has become an essential step in the design flow of today's complex integrated circuits. One effective technique that provides real-time visibility to the circuit under debug (CUD) is to monitor and trace internal signals during its normal operation. Typically, a large number of signals are tapped and a subset of them are selected to be observed in each debug process. These...
One of the main difficulties in post-silicon validation is the limited debug access bandwidth to internal signals. At the same time, SoC devices often contain dedicated bus-based test access mechanisms (TAMs) that are used to transfer test data between external testers and embedded cores. In this paper, we propose to reuse these precious TAM resources for real-time debug data transfer in post-silicon...
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