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We propose a surface potential-based polycrystalline silicon thin-film transistors (poly-Si TFTs) compact model considering a nonequilibrium state. A drain current model considers grain boundary (GB) trap-related physical phenomena: composite mobility of GB and intragrain, GB bias-induced mobility modulation, transient behavior because of carrier capture and emission at GBs, pinch off voltage lowering,...
This paper presents a surface potential based poly-Si thin-film transistor (SPT) model for SPICE which is formulated with both surface and grain boundary (GB) potentials calculated by Poisson equations. The drain current model includes GB induced mobility modulation, hot carrier effect, gate induced drain leakage, and trap dependent thermal leakage. The capacitance model is derived from physically...
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