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This work demonstrates a 3D vertical-gate (3DVG) NAND Flash with circuit-level techniques to overcome degradations in speed, yield, and reliability resulting from cross-layer process variations. The key enables include: (1) layer-aware program-verify-and-read (LA-PV&R), (2) layer-aware-bitline-precharge (LA-BP), and (3) a wave-propagation (WP) fail-bit detection (FBD) scheme. A fabricated 2-layer...
As NAND Flash device scales down, the source/drain junction engineering becomes a key factor for improving the short-channel effect, self-boosting program inhibit window, and cell reliability. In this work, the impact of trap-layer above junction (cut-ONO or non-cut ONO), Source/Drain Si recess, and junction doping are studied extensively for the 38nm half-pitch BE-SONOS charge-trapping NAND Flash...
A thorough study of the switching mechanism for WOX ReRAM gives clues about how to improve its performance and reliability. Consequently, a 60 nm WOX ReRAM is achieved with excellent characteristics - 50ns fast switching, 106 cycling endurance, large MLC window, low read disturb of >; 109, and excellent 150°C/2,000Hrs data retention. Furthermore, the oxidation of the TiN barrier into an insulating...
A novel solid-electrolyte based electrochemical induced conductive bridge (CB) resistive memory (ReRAM) is fabricated and characterized. The new device consists of a Cu-doped GeSbTe ion source, a SiO2 memory layer, and a TiTe ion buffer layer. The ion-buffer layer separates the Cu conducting path from the Cu-ion supply layer thus greatly increases the stability. This tri-layer device greatly improves...
Floating gate (FG) devices using barrier-engineered (BE) tunneling dielectric have been studied both theoretically and experimentally. Through WKB modeling the tunneling efficiency of various multi-layer tunneling barriers can be well predicted. Experimental results for FG devices with oxide-nitride-oxide (ONO) U-shaped barrier are examined to validate our model. Furthermore, a large-density array...
Bandgap-tunable SiON (oxynitride) tunnel barrier is developed to optimize the performance and reliability of BE-SONOS NAND Flash devices. The HTO O2 layer of the ONO tunnel barrier is replaced by SiON thin films with various refractive index (n) and thickness. We found that with n ≤ 1.72, SiON can provide excellent data retention comparable to conventional BE-SONOS. On the other hand, the erase speed...
Floating gate (FG) devices using barrier-engineered (BE) tunneling dielectric have been studied both theoretically and experimentally. Through WKB modeling the tunneling efficiency of various multi-layer tunneling barriers can be well predicted. Experimental results for FG devices with oxide-nitride-oxide (ONO) U-shaped barrier are examined to validate our model. Furthermore, a 1Mb test chip was fabricated...
The multi-level operation of WOx based RRAM has been investigated. Improvement of our WOx process has produced an extended linear R-V region for our devices. By adding an electrical forming process and a program-verify algorithm we have demonstrated stable 2-bit/cell operation, with potential for 3-bit/cell. The reliability of the MLC operation has been examined and very stable high temperature retention,...
The reliability of sub-40 nm SONOS NAND devices with various tunnel oxide thickness and FinFET structures are studied for future NAND Flash application. SONOS intrinsically has slow erase speed and high erase saturation for tunnel oxide ranging from 25 to 45 Aring. Furthermore, the endurance degradation occurs very early at low P/E<10, owing to the nature of electron de-trapping mechanism at tunnel...
A metal-high-k bandgap-engineered SONOS (MA BE-SONOS) with an additional SiO2 buffer layer is proposed. The thin SiO2 (5 ~ 6 nm) layer between the high-k (Al2O3) and nitride serves to prevent shallow trap generation. Contrary to the previously proposed MANOS or MA BE-SONOS devices using a simple high-k top dielectric, this composite structure eliminates the unstable high-k/nitride interface. Experimental...
The stress effect on the ONO stack layer in a two-bit SONOS-type memory cell is investigated. Our results show that P/E cycles induced stress will generate extra nitride, oxide, and interface traps in the ONO stack layer. Besides, these stress created traps are unstable and will be annealed by additional thermal treatment. Storage electrons escape from stress-created nitride and oxide traps and the...
In nitride storage flash memories, the high-VT state retention loss induced by field and temperature acceleration is compared between single cells and products. Our result reveal that the charge loss path is the same no matter which accelerating methods is used. The traps created at the bottom oxide during P/E cycling provide such leak paths. In addition, the annealing of interface states would play...
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