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The DOME MicroDataCenter, developed by IBM Zurich Research and ASTRON Netherlands Institute for Radio Astronomy, brings together the embedded and data-center computing worlds, resulting in the densest general-purpose computing capability with top energy-efficiency. This paper summarizes the entire 5 year project and illustrates how we went from an initial idea through obtaining funding for our small...
Novel hierarchical radially expanding micro-channel networks with pin fins have been proposed recently to enable high-performance embedded two-phase liquid cooling of two- and three-dimensional integrated circuits dissipating extremely high heat fluxes (of the order of 1kW/cm2) [1]. The effective design of such a complex two-phase liquid cooling architecture requires a comprehensive understanding...
In this paper, we present a novel thermal and electrical power-management solution for high-density electronic appliances, (such as a Microserver), that can handle a volumetric power density of up to 1350 W/dm3. The Microserver consists of a multitude of smart-phone-sized compute-node boards placed in vertical position with a pitch of 7.6 mm on a backplane board that fits into a 19"x2U rack unit...
Solar energy is typically converted into electrical energy or collected as thermal energy. Co-generation of electricity and low-grade heat allows a more efficient use of the solar spectrum. To this end, a prototype of a high-concentration photovoltaic thermal (HCPVT) system is demonstrated. It is based on low-cost optical concentrator materials, a high-efficient, densely-packed multi-cell receiver...
Integrated microfluidic power generation and power delivery promises to be a disruptive packaging technology with the potential to combat dark silicon. It essentially consists of integrated microchannel-based electrochemical “flow cells” in a 2D/3D multiprocessor system-on-chip (MPSoC), that generate electricity to power up the entire or part of the chip, while also simultaneously acting as a high-efficiency...
The soaring demand for computing power in our digital information age has produced, as an undesirable side-effect, a surge in power consumption and heat density for Multiprocessors Systems-on-Chip (MPSoCs). The resulting temperature rise results in operating conditions that already preclude operating all the cores at maximum performance levels, in order to prevent system overheating and failures....
To ensure functionality and integrity of electronic package interconnects, underfill materials are designed to meet a desired stiffness that bridges the thermal expansion behavior of die, substrates and interconnects. The underfill protects the interconnects from thermal strains and environmental influences. Recently, the thermal conductivity became a critical parameter too, to efficiently dissipate...
Three-dimensional (3D) stacking of integrated-circuit (IC) dies by vertical integration increases system density and package functionality. The vertical integration of IC dies by area-array Through-Silicon-Vias (TSVs) reduces the length of global interconnects and accordingly the signal delay time. On the other hand, the ongoing miniaturization trend of ICs results in constantly increasing chip-level...
Communication via narrow busses on large printed circuit boards slowed the efficiency improvements for PCs and servers causing increased power consumption. Low-power microservers continued to shrink reaching better efficiency. The focus on transistor scaling opened a communication bandwidth and latency gap and created two major roadblocks to further progress: power density and communication delays...
A novel semi-fluxless die-to-die bonding solution is presented, developed and successfully tested. Consisting of patterned thin film lead-free solder, this method was developed to meet the constraints given by the integration of state-of-the-art cooling structures into a 3D chip stack, such as minimizing the gap between the dies, sealing the active solder pads from a conductive coolant fluid and sealing...
We present a methodology for the formulation of percolating thermal underfills (PTUFs) with enhanced thermal conductivity for efficient heat dissipation between dies in 3D chip stacks. The methodology is based on the centrifugal filling of micron-sized powders in a confined space (defined by a solder ball array) to form a percolating particle bed, and on the formation of enhanced thermal contacts...
Ever increasing device density in electronic chips is beneficial for enhancing their computing efficiency. However, it also introduces severe challenges with respect to cooling solution which are indispensible for ensuring a reliable chip operation. Such steady miniaturization will soon render the traditional air cooling strategies futile and make the switching to liquid cooling inevitable. Superior...
Electronic packaging increasingly aims at copper pillars as an interconnect concept, because of their benefits for fine pitches, high aspect ratios, high electromigration stability and excellent thermal conductivity. The thermal expansion and high stiffness of the pillars remains a design challenge when building-up more copper volume close to the silicon die. Specific pillar geometries and structured...
In this work, we study the impact of the phonon thermal conductivity of Silver (Ag) and Gold (Au) on the interface resistance of metal-nonmetal contacts at room temperature. The thermal conductivity of both metals is determined for bulk and thin films of varying thickness using non-equilibrium molecular dynamics (NEMD) simulations. Likewise, we determine the thermal interface resistance due to phonons...
The following study focuses on the scalability of single- and two-phase cooling techniques to address the cooling constraints and requirements of future vertically integrated chips. Water and refrigerant R134a were considered for single- and two-phase cooling respectively during simulations. A parametric study based on fin height, fin width and channel width of multi-microchannel heat removal structures...
We demonstrate an advanced packaging approach with an embedded silicon micro-channel water cooler where the photovoltaic cell is electrically connected by a metallization on the silicon substrate. The backside of the silicon substrate contains the micro-machined fluidic channels thereby minimizing the thermal resistance compared to a state — of — the — art package. This leads to a reduced temperature...
Chip microscale liquid-cooling reduces thermal resistance and improves datacenter efficiency with higher coolant temperatures. This eliminates the need for chillers and allows the thermal energy reuse in cold climates. We demonstrated a 60°C hot water cooled supercomputers with twofold lower energy cost and a fivefold lower carbon footprint. Energy re-use for desalination and adsorption cooling allows...
Molecular dynamics simulations (MD) and the normal mode decomposition are used to determine the phonon relaxation times of acoustical and optical modes of germanium (Ge) at 1000 K and 1 atm. The relaxation times are calculated from the temporal decay of the autocorrelation function of the total energy of each normal mode in the [100] direction. Two sets of force field parameters are used to obtain...
Liquid cooling has emerged as a promising solution for addressing the elevated temperatures in 3D stacked architectures. In this work, we first propose a framework for detailed thermal modeling of the microchannels embedded between the tiers of the 3D system. In multicore systems, workload varies at runtime, and the system is generally not fully utilized. Thus, it is not energy-efficient to adjust...
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