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Embedded memories are widely used in low power System-on-Chip (SoC) applications. Low power performance can be optimized with process, circuits, architecture and system level co-development. In this paper, low power design considerations are described in advanced technology nodes to address memory leakage and active power dissipation. Memory bit cell design in context of process technology definition,...
A highly manufacturable embedded DRAM technology at 40 nm node is presented. This report provides the characterization data of 128 Mbit embedded DRAM test vehicle fabricated by 40 nm eDRAM 200 MHz low power process. The test vehicle is composed of 32 macros and each macro unit is 4 Mb with configuration 32 k × 128 bits. The process is cost effective and compatible to our low power Logic core process...
In this paper, the application of an asymmetric independent-gate MOSFET (IG-MOSFET) to the bit-cell structures of the SRAM schemes that were previously proposed using the symmetric IG-MOSFET is analyzed. In addition, a novel SRAM scheme with the asymmetric IG-MOSFET is proposed to improve read stability and writeability by controlling the back gates of pass-gate and pull-up transistors. New array...
This paper reports a 45 nm spin-transfer-torque (STT) MRAM embedded into a standard CMOS logic platform that employs low-power (LP) transistors and Cu/low-k BEOL. We believe that this is the first-ever demonstration of embedded STT MRAM that is fully compatible with the 45 nm logic technology. To ensure the switching margin, a novel "reverse-connection" 1T/1MT cell has been developed with...
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