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An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic capacitance sensing scheme, and dual metal plateline scheme - reduce bitline capacitance from 100 fF to 60 fF. As a result, a cell signal of ??220 mV...
An application that takes advantage of FeRAM characteristics is replacing current DRAM, which then becomes high-performance nonvolatile RAM cache. This improves system performance for many kinds of computer systems, including mobile PCs, cellular phones, digital video products, and storage systems such as SSDs. However, the highest capacity in nonvolatile RAMs that allow frequent cache reads and writes...
A scaling scenario of fully-depleted floating body cell (FBC) is demonstrated in view of signal margin for stable array functionality. Measurement and numerical simulation reveal that the Vth variation of cell array transistors is mainly attributed to the random dopant fluctuation in channel region. By setting the channel impurity concentration in the order of 1016cm-3 or lower, Gbit array functionality...
Floating body cell (FBC) is a one-transistor memory cell on SOI substrate, which aims high density embedded memory on SOC. In order to verify this memory cell technology, a 128Mb SOI DRAM with FBC has been designed and successfully developed. The memory cell design and the experimental results, such as the signal and the retention characteristics, are reviewed. The results of the fabricated SOI DRAM...
A 128Mb SOI DRAM with FBC (floating body cell) has been successfully developed for the first time. Two technologies have been newly implemented. (i) In order to realize full functionality and good retention characteristics, the well design has been optimized both for the array device and the peripheral circuit. (ii) Cu wiring has been used for bit line (BL) and source line (SL), which leads to increasing...
A dynamic latch sense amplifier/bit line replenishes "1" cells with holes lost during word line cycles and reduces the refresh busy rate. A multi-averaging method of dummy cells over 128 pairs of "1s" and "0s" enhances the sense margin and contributes to the 18.5ns access time. The 25.7ns virtually static RAM (VSRAM) mode is realized by taking advantage of the cell's...
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