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In this paper, we are interested in the Halogen-free (HF) impact on the reliability performance of portable electronic devices. Due to the trend of environment protection, the Halogen-free materials of solder paste, molding compounds, PCB and etc. have been widely discussed. When the material changes happen, the transition of failure modes in the board level can be expected, and the challenges are...
As technology scales, gate sensitivity to noise increases due to supply voltage scaling and limited scaling of the voltage threshold. As a result, power supply noise plays a greater role in sub-100 nm technologies and creates signal integrity issues in the chip. It is vital to consider supply voltage noise effects (i) during design validation to apply sufficient guardbands to critical paths and (ii)...
This paper describes an ESD verification methodology that is applied at several points in the design process. By identifying ESD reliability hazards at each step in the design flow, the amount of redesign needed to address ESD reliability issues is greatly reduced. The checker efficiently computes power bus parasitic resistances, allowing it to be used during floor planning when the library is unavailable;...
With the more reliability requirement increasing in the IC packaging for mobile product, the testing condition to simulate the service life of IC packaging on board will be emphasized, such as mechanical drop, temperature cycling, bending, vibration and so on. 4 point cyclic bending condition including different bending frequency and displacement to simulate actual service condition is defined in...
ESD reliability of MOS gate dielectrics and of input circuitry is investigated for a 90 nm CMOS technology. Performance degradation is observed at voltages lower than the breakdown voltage. It is found that the input transistor gate dielectric breakdown voltage depends strongly on the source-body voltage and, consequently, on the input circuit design.
Strain-Si field-programmable gate arrays (FPGA) is fabricated by using ultimate spacer process (USP) with a single capping stress liner. An overall 15% speed enhancement without compromising yield was obtained. The product reliability assessment, including HTOL, TCT, ESD (CDM and HBM) and latch-up, was performed simultaneously on USP and control parts. They show comparable product reliability and...
ESD-induced latent damage in CMOS integrated circuits has been thoroughly investigated after cumulative low-level ESD stress. A study of the latent damage for transistors at the package level has been performed with various kinds of ESD stress modes. The impact of latent damage on circuit performance degradation was also evaluated using a 64 Mb DRAM chip as a DUT.
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