The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents the design of an FPGA based real time video display size resolution conversion for QCIF to VGA. The architecture is based on a pre-computed memory mapping that facilitates reduction in memory size and latency. The scheme has been realized for real time resolution conversion of a QCIF video at 30 fps. The memory requirement has been reduced to 400 KB which is significantly lower...
High speed Elliptic Curve Cryptography (ECC) implementations on Field Programmable Gate Array (FPGA) are highly desirable for applications requiring high speed cost effective and flexible implementations of public key cryptography. Recently, many binary ECC hardware accelerators have been presented based on the Montgomery point multiplication by exploiting the underlying parallelism of the point multiplication...
With latest advancements in architecture, reprogram ability and availability of abundant on-chip resources, FPGAs (Field Programmable Gate Array) are used as hardware accelerators to speedup computationally intensive tasks with inherent parallelism. However non-availability of standard MATLAB and C/C++ computation routines and communication interface for general purpose programming restricted researchers...
Increase in use of nonlinear devices in power systems has caused serious harmonic pollution. There is always a need to measure these harmonics for power quality assessment and in cases for mitigating these harmonics. The problem of precision measurement becomes irksome because of effects of frequency deviation. Over the course of time a whole slew of digital signal processing algorithms have been...
This paper presents a method which can estimate frequency, power and phase of received signal corrupted with additive white Gaussian noise (AWGN) in large frequency offset environment. Proposed method consists of two loops, each loop is similar to a phase-locked loop (PLL). Proposed structure solves the problems of conventional PLL such as limited estimation range, long settling time, overshoot, high...
This paper proposes high data rate implementation of an adder on Field Programmable Gate Arrays (FPGA). Digital Signal processing applications are characterized by the data rate or the throughput of the system. Optimal hardware implementation on FPGA is differentiated from other hardware design platforms due to its fixed fabric and routing structure. Implementation of different adder architectures...
Ensuring integrity of run time software of the safety and safety related embedded systems used for protection, control and monitoring of nuclear power plants is an important issue. In this paper, we discuss the scheme being implemented on the in-house developed CPU board, to check integrity of run time software using cryptographic primitive. Our scheme uses off-line SHA-1 (Secure Hash Algorithm) software...
We propose a phase-locked loop (PLL) architecture, which reduces the double frequency ripple without increasing the order of loop filter. Proposed architecture uses quadrature numerically-controlled oscillator (NCO) to provide two output signals with phase difference of π/2. One of them is subtracted from the input signal before multiplying with the other output of NCO. The system also provides stability...
We are living in the era of minute by minute developments and new technologies, the demand of easy way of life is the talk of the day. Engineering industries are focusing on the projects which advance and facilitate their customers with comfortable and secure living. This paper discusses the most advanced idea of Domotics, in which the comprehensive controlling and monitoring of all home appliances...
This paper proposes a low power architecture for second order digital phase-locked loop (DPLL). High power consumption of DPLL results from using a look-up table (LUT) in implementing the numerically controlled oscillator (NCO). A new design for NCO is presented in which no LUT is used. Proposed architecture implemented using field programmable gate array (FPGA) consumed 15.44 mw at 100 MHz clock...
This paper presents an approach to reduce the power consumption of FPGA based digital circuits at FSM design level. The approach is based on clock gating technique. By using control signals at FSM level, we have limited the clock switching and other signals transitions in the system, leading to reduced dynamic power consumption of the systems. Our results have shown up to 7% reduction in dynamic power...
MEMOCODE Design Contest challenged teams to implement the architecture for a unique type of Deep Packet Inspector called CANSCID. This paper describes this unique problem statement, and the motivation for choosing it. This paper is followed by short descriptions prepared by individual teams detailing their particular approach to solving the problem.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.