The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Electrical properties of silicon-dot-based single-electron memory devices were investigated using numerical simulation. For an accurate calculation of tridimensional electron wave functions in the dots and in the dot-isolation surrounding the nextnano++ simulator was employed. Tunneling rates between the dot and other electrodes were calculated using a post-processing of the electron-state-specific...
In this paper we present an extensive comparison of tunneling device simulations versus experimental results. Different tunneling models were used to simulate long channel silicon on insulator tunneling field effect transistors. The results were compared to experimental results, which were taken from the literature. A calibrated parameter set of the dynamic NonLocal-Tunneling model is presented, which...
A simulation study of lithography induced layout variations in 6-T SRAM cells is presented. Lithography simulations of a complete 6-T SRAM cell layout, including active n+/p+ regions layer and poly-gate layer were performed. The smallest feature size was assumed to be 45 nm. 76 positions of the projector focus were simulated for each layer in total. TCAD simulations of 32nm single gate FD SOI MOSFETs...
We demonstrate the coupling of plasma reactor equipment simulation and feature-scale profile simulation for dry etching of silicon in a chlorine plasma. Equipment simulation delivers fluxes of ions and neutrals, as well as the angular characteristics of the ions. These quantities are fed into a feature-scale simulator based on a Monte Carlo approach for determining relevant quantities on the feature...
Source and relevance of process variations are briefly discussed. A combination of own lithography and commercial TCAD simulation software is applied to assess the impact of some of the most relevant variations occurring in lithography on the electrical properties of three kinds of CMOS devices with 32 nm physical gate length.
In this paper, a TCAD-based simulation study on lithography process-induced gate length variations has been performed. This study aims at evaluating fully depleted silicon on insulator (FD SOI) MOSFETs for next generation CMOS devices. Critical dimensions (CDs) have been obtained using rigorous lithography simulations. The impact of the resulting gate length variations on the electrical behavior of...
In this work, the influences of advanced annealing schemes, spike and flash annealing and combinations of them, on the electrical behavior of modern FD SOI MOSFETs have been investigated by numerical simulations. Process simulations have been performed for comparing the two-dimensional diffusion behavior of the dopants under the different annealing schemes. Device simulations have been performed for...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.