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The integration of a differential antenna in mainstream 65 nm CMOS was investigated. A 60 GHz prototype integrated circuit (IC) was developed, including a seal-ring and on-chip calibration structures. Measured results show excellent impedance matching properties over a 10 GHz bandwidth and a moderate antenna gain of −1.5 dBi. However, this is still a significant improvement as compared to state-of-the-art...
A self-rectifying bistable resistor named SR-biristor with capacitor-like MIM structure is presented for selector free, high density, low cost memory application. Stable hysteric I–V characteristics are utilized for data storage. The device exhibits following outstanding advantages: 1. Simple device structure with MIM configuration; 2. CMOS compatible processes and materials; 3. Self-rectifying and...
A fully reconfigurable SDR contains an RX, a TX, and 2 synthesizers for true multi-standard operation. A MEMS-enabled dual-band LNA proves the feasibility of switched antenna filtering for interference robustness. The baseband section is programmable in noise level and in bandwidth from 350kHz to 23MHz. The receiver has 6dB NF, -9dBm IIP3, and up to 90dB gain. Implemented in a 0.13μmum CMOS process,...
This paper investigates the scaling limit of CMOS supply voltage for maintaining the noise margin of NAND circuits subject to process tolerance induced threshold voltage variation. It is shown that for high performance (Vt/Vdd<1/3) decananometer CMOS devices with plusmn20% gate length tolerance and corresponding short-channel threshold roll-off, the supply voltage cannot be lower than 0.5 V in...
ESD protection strategies utilized in RF circuit applications in CMOS and BiCMOS technologies are investigated and the results are presented in this paper. The conventional approach using diodes with power clamp is compared with novel approaches such as plug-and-play passive elements and full or partial circuit-ESD co-design. The trade-offs are discussed from both RF and ESD point of views. Common...
An advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented. At 1V and off current of 100nA/mum, transistors have record currents of 1.21mA/mum and 0.71mA/mum for NMOS and PMOS respectively. This industry leading 65nm technology is currently in high volume manufacturing
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