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A new integration scheme is presented to solve device and manufacturing issues for extremely thin SOI (ETSOI) technology with high-k/metal gate. Source/drain and extensions are effectively doped by an implant-free process to successfully reduce series resistance below 200 Omegaldrm. A zero-silicon-loss process is developed to eliminate loss of thin SOI layer during gate and spacer processes, enabling...
We report a bias-dependent, nonlinear body resistance model suitable for accurate characterization of PD/SOI technology. This model is implemented in the surface potential based SOI MOSFET compact model PSP-SOI and experimentally verified for 65 nm PD/SOI technology node.
This paper reports recent progress on partially depleted (PD) SOI modeling using a surface potential based approach. The new model, called PSP-SOI, is formulated within the framework of the latest industry standard bulk MOSFET model PSP. In addition to its physics-based formulation and scalability inherited from PSP, PSP-SOI captures SOI specific effects by including a floating body simulation capability,...
The authors present a 65nm embedded DRAM cell (0.127 μm2 cell size) on unpatterned SOI fabricated using standard high performance SOI technology with dual stress liner (DSL). The cell utilizes a low-leakage 2.2-nm gate oxide pass transistor and a deep trench capacitor. A trench side wall spacer process enables a simplified collarless process. Connection to the buried plate is realized by silicided...
We report the first SOI MOSFET model that takes advantage of the recent progress in bulk MOSFET modeling. The surface-potential-based model is implemented without iterative loops, and includes physical modeling of the moderate inversion region and all small-geometry effects without relying on the traditional threshold-voltage-based formulation. The new model is verified for a 90 nm node process (40...
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