The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Ge n- and p-FinFETs with different interfacial layer ferroelectric HfZrOx (IL-FE-HZO) gate stacks have been demonstrated systematically by various annealing conditions for the first time. Microwave annealing (MWA) not only shows enhanced FE characteristics but also suppresses the gate leakage and Ge interdiffusion compared with conventional rapid thermal annealing (RTA). While HZO on Al2O3 IL results...
The FinFET architecture, introduced at the 22nm node [1], has delivered improved MOSFET electrostatics, which has enabled gate-length (LGate) scaling down to 48nm Contacted Gate Pitch (CPP) at the 7nm node [2], [3] (Fig. 1). Enhanced performance gains have been realized via the ‘Fin Effect’ (Weff/Fin-Pitch) boost, which provides improved drive current for a given capacitive load. However, limits on...
We demonstrate scaled high-Ge-content (HGC) strained SiGe pMOS FinFETs with very high short channel (SC) performance using a Replacement High-K/Metal Gate (RMG) flow, for the first time. A novel RMG gate stack process was introduced to create Ge-free interface-layer (IL) with excellent reliability and sub-threshold swing (SS) as low as 62mV/dec, the best reported to date for Si-cap-free SiGe FinFETs...
For the first time, the ion-vacancy-based bipolar RRAM has been demonstrated on HKMG stack of FEOL logic 14nm FinFET. A unit cell with two identical FinFETs, one serves as a control transistor and the other one is the storage with resistance switching. It is performed by the edge tunneling and with bipolar switching. More importantly, the sneak path issue in an AND-type array based on this FinFET...
In this work, we demonstrate a new concept for realizing high threshold voltage (Vth) E-mode GaN power devices with high maximum drain current (ID, max). A gate stack ferroelectric blocking film with charge trap layer, achieved a large positive shift of Vth. The E-mode GaN MIS-HEMTs with high Vth of 6 V shows ID, max 720 mA/mm. The breakdown voltage is above 1100 V.
This work provides breakthroughs in key technological modules for high performance and reliable 3D Sequential Integration with intermediate BEOL (iBEOL) in-between tiers. We demonstrate that (i) a high-quality solid phase epitaxy process is possible at 500°C, (ii) TiN native oxide removal prior to poly deposition leads to an improvement in gate stack reliability below 525°C and (iii) state-of-the-art...
An effect of adopting field plate (FP) technique in Gallium Nitride (GaN) high electron mobility transistor (HEMT) design is shown. The results of two-dimensional physical simulation of GaN HEMT with various FP design, taking into consideration the polarization effects, are represented. Results showed that optimized FP design allows to considerably decrease an electric field peak between gate and...
The industry's first 10nm low power high performance mobile SoC has been successfully ramped in production. Thanks to a thorough design-technology co-development, 10nm SoC is 16% faster, 37% smaller, and 30% lower power than its 14nm predecessor. The latest SoC features a gigabit class modem and is set to advance AR/VR, AJ, machine learning, and computing. 10nm FinFet technology scaling challenges...
We report the fabrication of short-channel FinFETs on InGaAs-on-silicon wafers using the aspect ratio trapping (ART) technique. We demonstrate excellent short-channel control down to 20 nm gate length due to scaled fin width down to 9 nm and reduction of parasitic bipolar effect (PBE). PBE that plagues III-V NFETs with gate-all-around (GAA) or III-V-on-insulator (III-V-OI) structures can be significantly...
This paper shows high-pressure anneal (HPA) as a performance booster for Si-passivated strained Ge (sGe) p-channel FinFET and gate-all-around (GAA) devices. Improved interface quality and hole mobility (∼600 cm2/Vs) are obtained on FinFET after HPA at 450°C. While Vth is tuned by ∼400 mV using TiAl work function metal (WFM), HPA-induced increases in Jg and NBTI are suppressed by barrier layer engineering...
The failure of power converters is currently the main reason of stopping for wind turbines. The unpredictable nature of wind power flow causes temperature swings to the semiconductor devices, which leads to additional thermal stresses and, eventually, unexpected failures. A suitable way to avoid this is using condition monitoring systems, which detect the degradation of the devices and reduce the...
Multi-flngered OTFTs, with staggered top-gate configuration have been fabricated on flexible polyethylene-naphtalate (PEN) substrates (100 μm thick). Inkjet printing technique has been used to setup the silver contacts, while the organic layers and the dielectric fluoropolymer have been deposited by spin-coating. The p-type polymeric semiconductor is a solution processed 6,13-bis(triisopropyl-silyletynyl)...
We present a stacked-FET monolithic millimeter-wave (mmW) integrated circuit Doherty power amplifier (DPA). The DPA employs a novel asymmetrical stack gate bias to achieve high power and high efficiency at 6-dB power back-off (PBO). The circuit is fabricated in a 0.15-µm enhancement mode (E-mode) Gallium Arsenide (GaAs) process. Experimental results demonstrate output power at 1-dB gain compression...
A compact nanoscale device emulating the functionality of biological synapses is an essential element for neuromorphic systems. Here we present for the first time a synapse based on a single ferroelectric FET (FeFET) integrated in a 28nm HKMG technology, having hafnium oxide as the ferroelectric and a resistive element in series. The gradual and non-volatile ferroelectric switching is exploited to...
A method for on-chip extraction of random telegraph noise (RTN) parameters from transistors is proposed. Exploiting the nature of exponential distributed RTN events, the proposed circuit enables the automatic extraction of mean RTN time constants from a large array of small-area transistors. The on-chip data processing provides a simplified measurement infrastructure, reduces the measurement time...
This paper highlights a 14nm Analog and RF technology based on a logic FinFET platform for the first time. An optimized RF device layout shows excellent Ft/Fmax of (314GHz/180GHz) and (285GHz/140GHz) for NFET and PFET respectively. A higher PFET RF performance compared to 28nm technology is due to a source/drain stressor mobility improvement. A benefit of better FinFET channel electrostatics can be...
Within the Dutch government the Gateway Review method has been adopted to facilitate a learning and helping perspective towards owners of high risk programs and projects with a substantial IT component. The current paper reports on findings from data analysis done on Gateway Review reports collected since the introduction of the method in the Ministry of Interior in the Netherlands. The conclusion...
We fabricated and in-depth characterized advanced planar and nanowire CMOS devices, strained by the substrate (sSOI or SiGe channel) and by the process (CESL, SiGe source/drain). We have built a novel access resistance (RACC) extraction procedure, which enables us to clearly evidence the strong impact of back-bias and strain on Racc (−21% for 4 V Vb and −53% for −1GPa stress on pMOS FDSOI). This is...
This work uses deep learning methods for intraday directional movements prediction of Standard & Poor's 500 index using financial news titles and a set of technical indicators as input. Deep learning methods can detect and analyze complex patterns and interactions in the data automatically allowing speed up the trading process. This paper focus on architectures such as Convolutional Neural Networks...
In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased Weff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.