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The special session covers the following: programmability based approach to post-silicon debug and rectification; an EDA tool chain for soft-error tolerant VLSI design; accurate and efficient SoC field test for failure prediction.
This paper presents a novel failure prediction testing technique that is applicable for system-on-chips (SoCs). Highly reliable systems such as automobiles, aircraft or medical equipments would not allow any interruptive erroneous responses during a system operation, which might result in catastrophe. Therefore, we propose a failure prediction delay testing technique that is applied during the time...
This paper presents a novel circuit failure prediction mechanism for high field reliability. On-line testing at a power-on/off time of a system detects the circuits' delay degradation that is caused by aging. Dedicated test vectors are applied using BIST architecture. Embedded ring oscillators are utilized to compensate the measured delay values for temperature or voltage shift. The concept and necessary...
A nondestructive evaluation system for detecting delamination between a chip and micro bumps in 3D-stacked structures is indispensable for highly reliable and low-cost manufacturing. In stacked structures, it is hard to inspect the adhesion condition of metallic bumps that connect a lower chip with an upper chip because most of the bumps are invisible. We have, therefore, proposed a new nondestructive...
Diagnosis has become a crucial technology for early debugging and yield improvement. However, the conventional diagnosis methods are not good at locating the defects that are not precisely expressed only with logical fault models. In this paper, we propose a novel defect diagnosis methodology, which is based on the evaluation of defect behaviors using physical information. We examine suspected nodes'...
Assessing the effectiveness of transition fault testing by the test coverage is misleading and can result on lower product quality. In reality, the actual timing of the test for each fault determines if a delay defect of a given size is detected or not. Transition tests that use actual circuit timings to create tests with the tightest possible timing detect more defects and have higher test effectiveness...
The three dimensionally stacked chip structures of electronic packages and modules have started to be used to maximize assembly density and to minimize signal delay. Since the thickness of the stacked silicon chips has been thinned to less than 100 mum, the local thermal deformation of chips has increased drastically because of the decrease of bending elasticity of the chips. In such a stacked structure,...
The quality of delay testing focused on small delay defects is not clear when traditional fault models are used. We therefore evaluated the feasibility of using the statistical delay quality model (SDQM) - which reflects fabrication process quality, design delay quality, test timing accuracy, and test pattern quality - by using a commercial automatic test program generation (ATPG) tool to apply it...
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