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We report a novel multi-level phase change random access memory (PCRAM) cell with a graded Ge2Sb2Te5 (GST) structure which enables multi-bit, high density storage. This work delves into the mechanism of the multilevel switching behaviour with both electrical as well as thermal analyses.
We report the first demonstration of III-V n-MOSFETs with self-aligned contact technology. The self-aligned contact was formed using a salicide-like process which is compatible with CMOS process flow. A new epitaxy process was developed to selectively form a thin continuous germanium-silicon (GeSi) layer on gallium arsenide (GaAs) source and drain (S/D) regions. Nickel was deposited and annealed to...
We report the first investigation of the impact of diamond-like carbon (DLC) high-stress liner on strained p-channel metal-oxide-semiconductor field-effect transistors (p-FETs) having silicon-germanium (SiGe) source-and-drain (S/D) stressor. The DLC exhibited a very high compressive stress of ~ 5 GPa. At a fixed Ioff of 1 x 10-7 A/mum, the DLC liner stressor contributed to a further 11% Ion enhancement...
In this paper, new technology options for boosting the performance of CMOS transistors pioneered by our group will be discussed. We focus on several new strain engineering techniques that were recently demonstrated for enhancing electron and hole mobilities in n-FET and p-FET, respectively. New applications of materials such as diamond-like carbon high-stress liner, silicon-carbon (Si:C or Si1-yCy...
We report the first demonstration of silicon-germanium (SiGe) impact-ionization MOS (I-MOS) transistors that feature a SiGe channel and a SiGe impact-ionization region. The lower bandgap of SiGe as compared to Si contributes to higher electron and hole impact-ionization rates, leading to avalanche breakdown at a much reduced source voltage and enhanced device performance. Both n-and p-channel I-MOS...
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