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Ustilago maydis expresses a number of proteases during its pathogenic lifecycle. Some of the proteases including both intracellular and extracellular ones have previously been shown to influence the virulence of the pathogen. However, any role of secreted proteases in the sporulation process of U. maydis have not been explored earlier. In this study we have investigated the biological function of...
The growing load demand and the higher penetration of renewable energy in a meshed DC grid in future may overload its existing transmission system, namely the Power Flow Congestion (PFC). The PFC can be mitigated either by installing additional transmission reinforcements or by better utilizing the existing transmission infrastructure. For the latter, this paper proposes a novel application of a controllable...
Recent advances in semiconductor process technology especially interconnects using Through Silicon Vias (TSVs) enable the heterogeneous system integration where dies are implemented in dedicated, optimized process technologies and stacked in a 3D form. TSMC has developed the CoWoS™ (Chip on Wafer on Substrate) process as a design paradigm to assemble silicon interposer-based 3D ICs. To reach quality...
Three-dimensional (3D) die stacking is an emerging integration technology which brings benefits with respect to heterogeneous integration, inter-die interconnect density, performance, and energy efficiency, and component size and yield. In the past, we have described, for logic-on-logic die stacks, a 3D DfT (Design-for-Test) architecture and corresponding automation, based on die-level wrappers. Memory-on-logic...
Using Through-Silicon Vias (TSVs) in three-dimensional stacked ICs (3D-SICs) has benefits in terms of interconnect density, performance, and power dissipation. For 3D-SICs, an extension of the Design-for-Test architecture based on die-level wrappers is required to enable pre-bond die testing as well as modular post-bond die and interconnect testing. This paper presents an approach that automates the...
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