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Modern SOCs may be composed of hundreds of individual physical modules, referred to as tiles. The total number of scan channels servicing these tiles often greatly exceeds the number of SOC device pins available to connect those channels to test equipment. Traditional reliance on a small number of pin-to-channel test mode configurations, predetermined in hardware, results in inefficient scan data...
Due to the development of novel Internet applications, Fault-tolerant needs to be improved and QoS (Quality of Service) routing capability is necessary in the network. Fault-tolerant QoS routing is one of the effective mechanisms to solve this problem. Considering the dynamic characteristic of network, we introduce the knowledge of fuzzy mathematics and probability theory to describe network state...
Dual-stripline is widely used in the computer systems to save printed circuit board (PCB) cost and achieve more compact form factor. Many design parameters can affect the overall performance of the dual-striplines. In this paper, the optimization of the dual-stripline design is discussed in detail, such as stackup selection, component breakout, etc. Theory analysis as well as Three-Dimensional full-wave...
In this paper, the signal integrity (SI) simulation and computer system electrical design flow is discussed. Traditionally, the SI analyses lead to a set of physical design rules that the printed-circuit board (PCB) and integrated circuit (IC) package designers rigorously follow in the layout to ensure the signaling performance meets the requirements. Such practice makes the signaling requirements...
High-speed traces routed in close proximity to a GPS patch antenna in a compact consumer electronic device could cause desensitization of the GPS receiver. Noise coupling mechanisms between the traces and the antenna are studied, together with the field patterns of the patch antenna. The insights gained in the understanding of the underlying coupling physics are further used to develop general trace...
Dual-stripline is gaining popularity in computer designs to save printed circuit board (PCB) cost and achieve more compact form factor. A key concern in dual-stripline design is the inter-layer crosstalk (ILC). In this paper, differential dual-stripline crosstalk is investigated, and a complete design strategy is provided. In addition to the conventional crosstalk mitigation techniques, an innovative...
In this paper, a fast signal integrity methodology using pseudo eye is introduced to characterize printed circuit board (PCB) channels. The pseudo eye and pseudo ratio are proposed as performance indicators of the channel. This methodology can be applied to not only the solution space check during the pre-layout design phase but also layout quality check before PCB manufacture. For pre-layout analysis,...
The board-level signal integrity, a new methodology to indicate the performance quality of a PCB channel, is introduced in this paper. Instead of the eye height and the eye width, the pseudo eye and amplitude ratio are defined as performance indicators of a PCB channel. The two applications of board-level signal integrity methodology are also given.
Basing on the requirements for high capacity and reliability of WMN data transmission, as well as the advantages of global optimization and highly self-organization of ant colony algorithm, we propose a cross-layer routing protocol based on ant colony algorithm, which is load-sensing and efficient. The protocol regards the nodes queue and frame transmission utility as a parameter measuring link quality,...
This paper presents an efficient method to solve the obstacle-avoiding rectilinear Steiner tree (OARSMT) problem optimally. Our work is developed based on the GeoSteiner approach in which full Steiner trees (FSTs) are first constructed and then combined into a rectilinear Steiner minimum tree (RSMT). We modify and extend the algorithm to allow obstacles in the routing region. For each routing obstacle,...
In this paper, we present an efficient method to solve the obstacle-avoiding rectilinear Steiner tree problem optimally. Our work is developed based on the GeoSteiner approach, modified and extended to allow rectilinear blockages in the routing region. We extended the proofs on the possible topologies of full Steiner tree (FST) to allow blockages, where FST is the basic concept used in GeoSteiner...
In todaypsilas VLSI designs, there can be many blockages in a routing region. The obstacle-avoiding rectilinear Steiner minimum tree (OARSMT) problem has become an important problem in the physical design stage of VLSI circuits. This problem has attracted a lot of attentions in research and several approaches have been proposed to solve this problem effectively. In this paper, we will present a heuristic...
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