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In this work we have investigated the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future applications. For the purpose of this paper we have simulated Si NWTs with six different cross-section shapes. However for all devices the cross-sectional area is kept constant in order to provide fair comparison. Additionally we have...
This paper proposes a low cost novel alternative testing approach to predict both DC and transient specifications of boost converters. Specifications such as load/line regulation are typically not measured in production because the parasitic inductances of the socket on the loadboard lead to voltage spikes that can destroy the device under test (DUT). To prevent potential damage to the DUT during...
An efficient approach is presented and demonstrated which enables the simultaneous simulation of the impact of several sources of process variations, ranging from equipment-induced to stochastic ones, which are caused by the granularity of matter. Own software is combined with third-party tools to establish a hierarchical simulation sequence from equipment to circuit level. Correlations which occur...
With continuous scaling in transistor size, there is demand to develop advanced FIB techniques for TEM failure analysis. Two techniques are reported here: 1) consecutive planar-cross section sample preparation for dual-direction TEM analysis and, 2) enhanced coating method for photo resists profile evaluation. Both the techniques have been successfully applied on deep sub-micron device issues which...
Nano Beam Diffraction has been used to analyze the local strain distribution in MOS transistors. The influence of wafer process on the channel strain has been systematically analyzed in this paper. The source/drain implantation can cause a little strain loss but the silicidation step is the key process in which dramatic strain loss has been found.
Increasing CMOS device variability has become one of the most acute problems facing the semiconductor manufacturing and design industries at, and beyond, the 45 nm technology generation. Most problematic of all is the statistical variability introduced by the discreteness of charge and granularity of matter in transistors with features already of molecular dimensions [i]. Two transistors next to each...
For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2. Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V Vdd with a low cost process. With this high performance transistor,...
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