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A high-energy-efficiency wireless communication link scheme is proposed for portable medical applications with strict resource constraints. The scheme is especially optimized for the application systems with the star-topology master-slave network, i.e., the network formed by a portable data-logger (master) and several sensor nodes (slaves). The proposed scheme eliminates “non-effective” operation...
A novel CMOS temperature sensor embedded in a passive UHF RFID tag is presented. The sensor consists of a temperature-to-current converter, two current-starved ring oscillators and two digital counters. High power consumption band-gap voltage references and traditional ADCs are not used for low power design. Post-layout simulation show that the power consumption is 0.64 μW with a supply voltage of...
A 15-bit 3rd order ΔΣ modulator is presented. The feed forward topology with 18-level quantizer is adopted. The signal swing of the 1st integrator is effectively suppressed. A current-mirror OTA with 42dB DC gain is used in the 1st integrator. Chop stabilization is employed to remove the flicker noise. The prototype is fabricated in 0.18μm CMOS. The active die area is 0.85×0.85mm2. The power consumption...
Field programmable gate arrays (FPGAs) allow the same silicon implementation to be programmed or reprogrammed for a variety of applications. It provides low NRE (non-recurring engineering) cost and short time to market. As CMOS technology continue to scale down to nanometer, increased power consumption and worsened process variation become crucial constraints for FPGAs. The survey reviews the process...
This paper presents in details the architecture and most of RF front-end building blocks of a fully integrated passive radio frequency identification (RFID) transponder operating at UHF 902 MHz to 928 MHz. A novel architecture for the transponder IC and a new low power on-off keying (OOK) demodulator are proposed in this paper. For realizing the system, a low power CMOS full-wave rectifier achieving...
A function-based memory partitioning (FBMP) method is proposed and adopted in a low power digital signal processor (DSP) for cochlear implants (CIs). Based on pre-analysis of intended application programs, instructions and data are divided into functional groups with different accessed frequencies. Monolithic instruction and data memories are then partitioned into multiple sub-banks and assigned to...
A 13-bit CMOS pipeline analog-to-digital converter (ADC) with improved sampling circuits is proposed. In the first pipeline stage, the high frequency performance of the sampling circuit is improved by reducing the on-resistances of the switches and the time skew between the sampling capacitors and the comparators. In the subsequent stages, the conventional sampling circuit is modified for low power...
This paper presents a novel space division transponder anti-collision algorithm for RFID system, which has been implemented in a passive transponder. Working at 915 MHz carrier frequency with 4W effective isotropic radiated power (EIRP) from a reader, the tags can be distinguished by their diverse distances to the reader if the distance difference is larger than 0.11 m with communication range from...
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