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A unified FinFET reliability model including high K stack dynamic threshold (HKSDT), hot carrier injection (HCI), and negative bias temperature instability (NBTI) has been developed and verified by experimental data. The FinFET-based circuit performances are simulated and compared under these reliability issues by HSPICE simulator after the inclusion of the presented model.
A modeling study of dynamic threshold voltage in high K gate stack is reported in this paper. Both slow transient (STCE) and fast transient charging effect (FTCE) are included in this model. Finally, this model is applied in FinFET reliability and circuit performances are simulated. The result shows that, the drain circuit (Id) degradation in FinFET is much more obvious than normal MOSFETs with the...
Reliability of FinFETs is studied in this paper using the forward gated-diode generation-recombination (G-R) current. It is observed that the stress induced interface states result in the shift of the peak G-R current (??Ipeak) in the body current (Ib) versus gate voltage (Vg) characteristic, therefore the variation of interface states with stress time was calculated. In the hot carrier injection...
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