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A 16Mb MRAM based on 0.13mum CMOS and 0.24mum MRAM process achieves a 34ns asynchronous access and 100MHz synchronous operation, compatible with pseudo-SRAM for mobile applications. By implementation of FORK wiring scheme, the cell efficiency is raised to 39.9% and the disturb robustness of half-selection state is improved
A 5-V-only CMOS 512 K*8 EEPROM (electrically erasable and programmable read-only memory), which achieves 10/sup 4/ cycle endurance using a NAND-structured cell, is discussed. The main features are a programming technique appropriate to the NAND structured cell and a dynamic sense amplifier. The NAND structured cell arranges 8 bits in series, sandwiched between two select transistors. The first transistor...
Novel device technologies for a 5-V-only EEPROM (electrically erasable programmable read-only memory) with a NAND structure cell are described. By applying half of the programming voltage to unselected bit lines and a successive programming sequence, the NAND structure cell keeps a wide threshold margin. A high-voltage CMOS process realizes reliable programming characteristics. The reliability of...
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