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The authors describe a 4-Mb NAND-EEPROM with tight <e1>V</e1>t (threshold voltage) distribution which is controlled by a novel program verify technique. A tight <e1>V</e1>t distribution width of 0.6 V for the entire 4-Mb cell array is achieved, and read margin is improved. A unique twin p-well structure has made it possible to realize low-power 5-V-only erase/program operation...
A 5 V-only 4 Mb NAND EEPROM (electrically erasable programmable read-only memory) has been successfully developed. The EEPROM has on-chip high-voltage generators, so the system needs only a 5 V power supply. The block-page erase/program mode realizes high-speed programming. On-chip test circuits provide high reliability. The NAND EEPROM has many applications for compact microcomputer systems, which...
A 5-V-only CMOS 512 K*8 EEPROM (electrically erasable and programmable read-only memory), which achieves 10/sup 4/ cycle endurance using a NAND-structured cell, is discussed. The main features are a programming technique appropriate to the NAND structured cell and a dynamic sense amplifier. The NAND structured cell arranges 8 bits in series, sandwiched between two select transistors. The first transistor...
The authors describe a novel accurate model and numerical analysis of subbreakdown phenomena due to band-to-band tunneling in a thin-gate-oxide n-MOSFET. Subbreakdown I-V characteristics are calculated for various oxide thicknesses. The results agree with experimental results over a wide range of subbreakdown current from 10/sup -12/ A to 10/sup -6/ A. The numerical analysis based on this model has...
Novel device technologies for a 5-V-only EEPROM (electrically erasable programmable read-only memory) with a NAND structure cell are described. By applying half of the programming voltage to unselected bit lines and a successive programming sequence, the NAND structure cell keeps a wide threshold margin. A high-voltage CMOS process realizes reliable programming characteristics. The reliability of...
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