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This paper introduces a fully-integrated wireline transmitter operating at 40Gb/s. The transmitter incorporates a combiner of 64:1 MUX and 2-tap Feed-Forward-Equalizer (FFE). The transmitter is achieved in 65nm CMOS technology. The simulation results show that the proposed transmitter can work at 40Gb/s with a −11dB RLGC channel. The simulation power consumption is 76 mW under 1.08V supply, and the...
This paper introduces a fully-integrated wireline transmitter operating at 28Gb/s. The transmitter incorporates a 3-tap Feed-Forward-Equalizer (FFE) with Flipflop-based delay to equalize the channel. T-coil networks are used with ESD protection circuits at transmitter's output to realize impedance matching and bandwidth enhancement. The transmitter is fabricated in 65nm CMOS technology. The measurement...
A 4×20-Gb/s source-series-terminate (SST) transmitter with 2-tap FFE and far-end crosstalk (FEXT) cancellation is presented. The FFE and crosstalk canceller (XTC) are merged together with the SST driver. The proposed transmitter architecture with divider-less clock generation can not only guarantee the timing requirement for the highest-speed serialization under PVT variation, but also save a lot...
This paper presents a 50Gbps half rate SerDes transmitter with automatic serializing time window search. By implementing a serializing time window search loop, the serializing timing is guaranteed and circuits running at highest speed such as latches for retiming and clock tree buffers for delay matching are eliminated. Fabricated in 65nm CMOS technology, the transmitter running at 50Gbps consumes...
This paper describes the design of a source-synchronous transmitter in 65nm CMOS technology. The transmitter consists of five data lanes plus one forwarded clock lane. Every single lane works at 10Gb/s. The clock distribution path is carefully designed to ensure the synchronous of the divided clock in every data lane. And this design is power efficient by optimizing the structure of MUX. Furthermore,...
Aiming at the specified protocol of EPC global Class-1 Generation-2, design considerations are expatiated to a novel structure of transmitter front-end for mobile RFID reader with 0.18 um CMOS process. The transmitter front-end consists mainly of an up-conversion mixer, a linear power amplifier (PA) and a non-linear PA. Controlled by the reader's working status, the implemented scheme can transmit...
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