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In this paper, Electrostatic-Discharge (ESD) reliability study of 45-V HV pLDMOS devices with the source-side discrete islands is investigated. A pure pLDMOS transistor is always frail in ESD harms (It2= 0.107-A). However, if a pLDMOS device with two embedded SCRs (drain side npn-arranged); the corresponding It2 current can be upgraded to 0.644-A. Furthermore, as a pLDMOS-SCR (npn-arranged stripe...
For the anti-ESD reliability consideration, the drain-side with super-junction structures and “npn” embedded type SCRs of nLDMOS transistors are investigated in this paper. From the experimental data, we can find that the layout manner of super-junction types in the drain-side have positive impacts on the anti-ESD capability. On the other hand, as the drain-side added another item i.e. an embedded...
The impact of layout-type dependences on anti-ESD robustness in a 0.25 μm 60 V process will be investigated in this paper, which included the traditional striped-type nLDMOS, waffle-type nLDMOS, and nLDMOS embedded with a pnp-manner SCR devices. Then, these nLDMOS devices are used to evaluate the influence of layout architecture on trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown...
In this work, we present a single-chip design for the three-phase brushless DC motors (BDCM) system, and which is implemented by a 0.35 μm 3.3 V CMOS process. A mixed-signal IC will be accomplished by the implementation of analog circuit and digital circuit in the same chip. Eventually, this chip system includes an analog circuit (Hall signal amplifier), a digital circuit (logic process block), and...
In this paper, a floor plan design application for multilayer substrate is implemented. The simplified evaluation method for thermal, routing and area criterions are discussed and implemented. And then normalize the criterions before the substrate floor plan such that the settings for substrate floor plan are reasonable. And finally, the calculated routing length, area and ANSYS thermal simulation...
This work is referring to the nMOSFET singer-finger, multi-finger structures under the Electro-Static Discharge (ESD) zapping, and to evaluate the current distribution situations. By using the TCAD and HSpice, because of the internal parasitic resistance differences in each one finger, which can cause non-uniform turned on. Meanwhile, with different interior parasitic capacitor on each nMOSFET type,...
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