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A drain current model with improved computational efficiency for double-gate (DG) MOSFETs is presented in this paper. Based on our previously proposed potential model, the drain current model is obtained with the implementation of an improved calculation method and the computation efficiency is substantially enhanced. 2-D device simulation (TCAD) is extended to verify the proposed model. In addition,...
This paper presents a novel input/output interface circuit for field programmable gate array (FPGA) devices, which has high voltage tolerant and PCI compliant capabilities. In the proposed circuit, dynamic gate and N-well bias technology is used to eliminate gate-oxide overstress and Pad to output supply (Vcco) leakage current when FPGA devices operate with high voltage input, and to ensure that over-voltage...
A generic DG MOSFET analytic model with vertical electric field induced mobility degradation effects is proposed and verified in this paper. It is shown that the proposed model is valid for different operation modes including symmetric DG (sDG), asymmetric DG (aDG) and independent DG (iDG). Extensive two-dimensional (2-D) device simulation is performed to verify the proposed model.
ULTRA-SOI is a new generation of the channel-potential-based non-charge-sheet model for the dynamic depletion (DD) Silicon-On-Insulator (SOI) MOSFET, developed by TSRC group in EECS department of Peking University with many year efforts. The model is formulated with a fully physical derivation from the Poisson's equation to solve the potential along the vertical direction of the silicon film. The...
This paper presents a new and more accurate potential based model for bulk MOSFET compared to the traditional charge-sheet surface potential model. The channel potential of the bulk MOSFET is obtained by solving Poisson equation and an accurate current expression is obtained base on it. Taking Pao-Sah model as a standard, the relative errors of the charge-sheet model may be as large as 4% in the saturation...
In this paper an analytic model for Ge/Si core/shell nanowire MOSFETs (NWFETs) is developed. First, the electrostatic potential and charge model are derived out from classical device physics. Then the drift-diffusion drain current model is obtained and verified by comparisons with the numerical simulation. The ballistic current model is obtained with the approximately described quantum-mechanical...
This paper presents modeling nanometer MOSFETs by a neural network approach. The principle of this approach is firstly introduced and its application in modeling DC and conductance characteristics of nano-MOSFET is demonstrated in details. It is shown that this approach does not need parameter extraction routine while its prediction of the transistor performance has a small relative error within 1%...
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