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We present a new scheme of buffer implementation in through-silicon via (TSV) based 3D circuits at early layout design stage for total delay minimization. For optimal buffer insertion at floorplanning level, it is important to incorporate more accurate and realistic estimation of interconnect delay and power. Early prediction of delay and power leads to better design decisions, overall timing closure...
We propose a novel floorplanning algorithm for 3D ICs with through-silicon vias (TSVs) that directly optimizes delay due to wires and TSVs. We include the non-negligible impact of area occupied by TSVs, perform nets-to-TSVs assignment, and use physical dimensions of TSVs and wires for delay calculations. Our floorplanning is based on co-placement of TSV islands with circuit blocks and is performed...
A very important challenge in designing through-silicon via (TSV)-based 3D ICs is to accurately estimate, through all stages of the physical design, the interconnect delay which is strongly dependent on the layout of 3D IC. The earlier in the design process and more accurate it can be done; the better design decisions can be made. Incorporating an optimal buffer insertion approach in the early layout...
3D technology facilitates reduction in wirelength by vertically stacking dies. Through-silicon-vias (TSVs) are used to connect inter-die signals, and the RC value of a single TSV depends on TSV dimensions, technology and used materials. The impact of TSVs on the delay also depends on the interaction between neighboring TSVs, on the length of wires connected to TSVs, and physical parameters of metal...
3D-IC technology discussed in this paper is based on vertical stacking of dies connected by through-silicon-vias (TSV). Vertical stacking helps reducing the wirelength but TSVs occupy space on device layers and their actual positions, arrangement, and physical properties determine the total wirelength. They also introduce thermo-mechanical stress that alters properties of devices that are close to...
3D-IC design facilitates reduction in wirelength by vertically stacking dies. Through-silicon-vias (TSVs) are used to connect inter-die signals. The dynamic power consumption of interconnects in 3D-IC is contributed by wires, buffers and TSVs. The delay in interconnects for 3D-IC is greatly influence by TSV capacitance. In this paper we propose TSV capacitance-aware 3D floorplanning to reduce the...
3D integration is considered as one of the most promising solutions to improve energy efficiency of heterogeneous ICs. We use floorplannning tools to evaluate power consumption related to inter-block connections for digital ICs implemented as 2D and 3D systems. We focus on 3D stacking using through-silicon-vias (TSVs). We evaluate contributions of wires, buffers and TSVs based on information available...
We present a fast evolutionary algorithm using sequence pair (SP) representation for hard block fixed-outline and non-rectangular floorplanning. We use dummy modules to represent various non-rectangular floorplans. The dummy module locations on layout and the feasibility of candidate solutions are verified directly on the SP representation without generating constraint graphs or floorplans. It significantly...
We analyze delay, dynamic and leakage power of TSV based 3D-ICs under stress-induced mobility and threshold voltage changes. It is shown that variations in MOS device characteristics can influence the overall chip performance depending on the number of affected devices. We also analyze the impact of these changes on the reliability of circuit designs. Mean time to failure (MTTF) is calculated under...
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