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Arbiter Physical unclonable function (A-PUF) with exponential number of challenges is an ideal candidate to realize lightweight and robust device authentication in Internet of Things applications. Unfortunately, it is particularly difficult to attain highly reliable responses and increase its modeling attack resistance simultaneously. This paper presents an approach to reduce the vulnerability of...
Physical Unclonable Function (PUF) has now become a core lightweight hardware-intrinsic cryptographic primitive for device identification and authentication to secure edge computing in Internet of Things (IoT). The main challenge in most delay-based PUF implementations is the rival of response uniqueness and reliability. Due to routing constraint, implementation of delay-based strong PUF on FPGA tends...
Recent hardware implementations of fully homomorphic encryption (FHE) exploit very high cardinality arbitrary moduli sets to parallelize large integer arithmetic. However, the benefit they gained are heavily offset by the slow residue-to-binary conversion due to the large modulo operations and limited number theoretic properties of arbitrary moduli. This paper presents a fast residue-to-binary (R2B)...
This paper presents a new secret-hiding method for watermarking or fingerprinting the digital signal processing circuits. It uses the characteristic noise introduced by the truncation or rounding off of the results of arithmetic operations to distinguish between the otherwise identical circuits. Watermark is physically and functionally integrated with the circuit and can be extracted dynamically....
One main problem encountered in the FPGA implementation of Arbiter based Physical Unclonable Function (A-PUF) is the response instability caused by the metastability of delay flip-flop. This paper presents a new multi-arbiter approach to extract more entropy to extend the number of response bits to a single challenge. New multi-arbiter schemes based on the insertion of either a four-flip-flop arbiter...
Application developers are now turning to field-programmable gate array (FPGA) devices for solutions of small to medium volume due to its post-fabrication flexibility. Unfortunately, the existing upfront intellectual property (IP) licensing model for FPGA based third-party IP cores is economically unattractive. The IP bitstreams in transaction are also vulnerable to cloning, misappropriation and reverse...
Elliptic curve cryptography (ECC) is a good candidate for protecting secret data on resource constrained devices. FPGA-based implementations of its main operation, i.e., scalar point multiplication, have gained popularity for their apparent speed advantage over the software counterparts. This paper presents a simple design of point multiplication that minimizes the occupied FPGA resources while maintaining...
The modus operandi of the upfront intellectual property (IP) licensing model is impractical for the developers of small to medium volume of field-programmable gate array (FPGA)-based applications. The FPGA IP market is in dire need for a more competitive and secure IP licensing scheme to flourish. In this paper, a pragmatic security protocol that could support the licensing of IP cores on a per-device...
This paper addresses the direct optimization of pipelined adder graphs (PAGs) for high speed multiple constant multiplication (MCM). The optimization opportunities are described and a definition of the pipelined multiple constant multiplication (PMCM) problem is given. It is shown that the PMCM problem is a generalization of the MCM problem with limited adder depth (AD). A novel algorithm to solve...
The research on optimization of Multiple Constant Multiplication (MCM) during the last two decades has been focusing mainly on common subexpression elimination and reduced adder graph algorithms when bit-parallel computation is required. The advancement of FPGA technology enables the implementation of complex MCM instances on FPGA, but the shift-and-add network implementation does not make full use...
The paper starts with an overview of distributed arithmetic (DA) and n-dimensional reduced adder graph (RAG-n) multiplierless filter design methods. Since DA designs are table-based and RAG-n designs are adder-based, FPGA synthesis design data are used for a realistic comparison. Benchmark FIR filters (Goodman and Carey, 1977) of length 11 to 63 are compiled. For a wide set of realistic design examples,...
Modular multiplication in Galois Fields - GF(p) and GF(2m ) is an ineluctable and time stumbling block in public key cryptosystems. Montgomery modular multiplication has emerged as a VLSI efficient implementation of this operation. In this paper, a new scalable and pipelined Montgomery multiplier architecture that unifies the two important finite fields, GF(p) and GF(2m), is presented. The proposed...
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