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The trade-off between transmission performance and hardware implementation in application-specific integrated circuits of digital backpropagation (DBP) in coherent 32 GBd polarisation-division multiplexing 16 quadrature amplitude modulation is analysed. The reach is optimised for different DBP implementations under constraints of 16 and 28 nm complementary metal–oxide–semiconductor (CMOS) technology...
A 50-Gb/s differential transimpedance amplifier is realized in a standard 65nm CMOS process, which exploits asymmetric transformer peaking technique for bandwidth extension and employs a modified regulated-cascode input stage with a shunt-feedback common-source amplifier for differential signaling. Measured results demonstrate 52-dBΩ transimpedance gain, 50-GHz bandwidth for 50fF photodiode capacitance,...
This paper presents a 3.1-5 GHz IR-UWB CMOS transceiver designed using 0.18μm CMOS technology. The LNA stage includes a frequency tunable load and digitally controlled notch filter allowing the three channel selection. To remove the bulky and lossy external balun, the receiver contains a single to differential circuit embedded in LNA stages. The transmitter adopts a pulse generator using the switched...
This paper presents a wide-band RF front-end with linear active notch filter covering both T-DMB and DVB-H. A single to differential converter with the low amplitude/phase error and 6dB step RF VGA using the capacitor are implemented. Also, highly linear and Q-enhanced tunable active inductor is proposed. The linear active notch filter rejects GSM band up to 23dB and achieves 20dB linearity improvement...
A Coherent IR-UWB transceiver covering low band of UWB spectrum from 3.1 to 5GHz is designed using 0.18 μm CMOS technology. The receiver contains a single to differential circuit embedded in LNA stages to remove the bulky external balun. The transceiver includes 3-stage LNA, VCO based pulse generator, multiplier, VGA, and comparator. The gain of LNA stage is 30dB and has NF lower than 4dB. The transmitted...
In this work, an IR-UWB RF Receiver compliant with 802.15.3a standard is fabricated on a single chip using 0.18um CMOS technology. The Receiver chip covers 3-5GHz lower band and 3-stage LNA is realized without on-chip inductor, which reduces the chip size dramatically down to 1.8mmx 0.9mm. The input signal is differential type in order to improve the immunity from common mode noise and undesired harmonic...
The chaotic UWB RF transceiver system is designed in CMOS 0.18 m technology with flexible chaotic signal generation. Although the chaotic UWB technology is expected as a promising solution for near-range connectivity services, it has a limitation for commercial applications due to a fixed-band chaotic signal generator. In this paper, the noble flexible chaotic signal generator with adjustable frequency...
The chaotic UWB RF transceiver system is designed in CMOS 0.18 mum technology with flexible chaotic signal generation. Although the chaotic UWB technology is expected as a promising solution for near-range connectivity services, it has a limitation for commercial applications due to a fixed-band chaotic signal generator. In this paper, the noble flexible chaotic signal generator with adjustable frequency...
This paper presents a low power CMOS transmitter for UHF mobile RFID applications, in a 0.18-mum CMOS technology. It uses a directional coupler in front of an antenna to reduce transmitter carrier leakage at receiver front-end and to be integrated into mobile handset with a single antenna. It adapts a direct conversion transmitter and consists of low pass filter, variable gain amplifier, up-conversion...
A UHF mobile RFID single-chip reader is implemented in a 0.18mum CMOS technology. The reader IC integrates an RF transceiver, a digital baseband modem, an MPU and host interfaces in 4.5 times 5.3mm2. The RF transceiver draws 61mA from a 1.8V supply and achieves an 8dBm P1dB, an 18.5dBm IIP3, and a 4dBm TX power.
The application of power gating circuits to semicustom design based on standard-cell elements is limited due to the requirement of customizing cells that are tailored for power gating or the requirement of customizing physical design methodologies for placement and power network. We propose a new power network architecture that enables use of conventional standard-cell elements. A few custom library...
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