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Due to the requirement of high data transmission rate, bandwidth has become an important performance parameter for high speed VLSI design. In order to have the maximum data transfer possible through the on-chip data buses, the bandwidth of the interconnect has to be precisely modeled. At very high frequency (of the order of few GHz) both inductance and conductance matrices become equally important...
Soft input soft output (SISO) decoders iteratively exchanging intermediate results (extrinsic information) between themselves lie at the core of turbo decoder architectures. The implementation architecture could be serial, parallel or network on chip (NoC) based. In this paper, we present a technique for bit-width reduction of exchanged extrinsic information and analyze the impact of it for different...
This paper describes an integrated network-on-chip architecture containing 80 tiles arranged as an 8x10 2-D array of floating-point cores and packet-switched routers, both designed to operate at 4 GHz. Each tile has two pipelined single-precision floating-point multiply accumulators (FPMAC) which feature a single-cycle accumulation loop for high throughput. The on-chip 2-D mesh network provides a...
A five-port two-lane pipelined packet-switched router core with phase-tolerant mesochronous links forms the key communication fabric for an 80-tile network-on-chip (NoC) architecture. The 15FO4 design combines 102 GB/s of raw bandwidth with low fall-through latency of 980 ps. A shared crossbar architecture with a double-pumped crossbar switch enables a compact 0.34 mm2 router layout. In a 65nm eight-metal...
A 275mm2 network-on-chip architecture contains 80 tiles arranged as a 10 times 8 2D array of floating-point cores and packet-switched routers, operating at 4GHz. The 15-F04 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. The 65nm 100M transistor die is designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.
A multicore processor in 65-Nm technology with 80 single-precision, floatingpoint cores delivers performance in excess of a Teraflops while consuming less than 100 W. A 2D on-die mesh interconnection network operating at 5 GHz provides the high-performance communication fabric to connect the cores. The network delivers a bisection bandwidth of 2.56 Terabits per second and a per hop fall-through latency...
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