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A novel design scheme using neuron-MOS dynamic literal circuit and double pass-transistor logic(DPL), to realize voltage-mode dynamic ternary logic gate, is proposed. The double pass-transistor used to transmit ternary signal is controlled by the output of the dynamic literal circuit to realize ternary logic function. The complementarity and duality principles for generation of dynamic ternary complementary...
A neuron-MOS-based dynamic circuit scheme with two-phase clocks for realizing voltage-mode quaternary logic, is proposed. The dynamic quaternary inverter and literal circuits are designed, and the standard CMOS process with a 2-ploy layer is adopted without any modification of the thresholds. In the proposed circuits, the problem of floating output nodes is solved. The proposed circuits have some...
A novel adjustable Schmitt trigger using multiple-input floating-gate MOS(FGMOS) threshold inverter is presented. The simple circuit consists of one n-channel FGMOS, one p-channel FGMOS and a conventional CMOS inverter. The different hysteresis voltages can be achieved by varying the ratio of capacitive coupling coefficients. By only changing the values of external input control signals, the hysteresis...
A new structure of voltage-mode binary Schmitt trigger with n-channel neuron-MOS device is designed. In this presented circuit scheme, the hysteresis window of the Schmitt circuit can be shifted by adjusting the value of the external control signal, and the hysteresis voltage can be verified by choosing the different ratio of capacitive coupling coefficients. Besides, the proposed Schmitt circuit...
A neuron-MOS-based dynamic circuit scheme with two-phase clocks for realizing voltage-mode multiple-valued logic(MVL), is proposed. The dynamic ternary inverter, literal circuits, and quaternary inverter are designed, and the standard CMOS process with a 2-ploy layer is adopted without any modification of the thresholds. In the proposed circuits, the problem of floating output nodes is solved. The...
A new true-single-phase clocked (TSPC) full-adder using floating-gate MOS (FGMOS) transistor is presented. In this new design scheme, the logic tree for the sum-generate circuit is realized using only an n-channel multiple-input FGMOS transistor, and the logic for the carry-generate circuit is realized using a complementary FGMOS-based inverter. By using FGMOS transistors, the circuit structure can...
A new dynamic circuit scheme to realize voltage-mode ternary circuit using floating-gate MOS (FGMOS) transistor is presented. The dynamic ternary inverter and literal circuits with the less complex structure are designed, and they can be implemented by the standard CMOS process with a double-poly layer without any modification of the thresholds. In the proposed scheme, the circuit output is always...
Dynamic circuits using n-channel multiple-input floating-gate MOS(FGMOS) transistors to realize binary and ternary logic are presented. In binary domino circuits, the n-channel FGMOS transistors are used to replace the nMOS logic block to simplify the circuit structure. By using the advantage that voltage signals are easy to be added by means of floating gate in multiple-input FGMOS transistor, a...
A No Race (NORA) dynamic logic using neuron-MOS transistor is presented. The circuit is designed using the n-channel neuron-MOS transistor instead of the nMOS logic block or pMOS logic block in the conventional NORA dynamic logic circuit. The proposed full-adder shows that the logic block of NORA circuit can be simplified by utilizing neuron-MOS transistor. A simple synthesis technique of the n-channel...
Two new differential flip-flops using neuron-MOS transistors are presented, including one-latch single edge-triggered(IL-SET) flip-flop and one-latch double edge-triggered(IL-DET) flip-flop. In the new differential flip-flops, a pair of n-channel neuron-MOS transistors is used to replace the nMOS logic tree in the conventional differential flip-flops. The construction of the circuits has been simplified...
Novel differential flip-flops using neuron-MOS transistors are presented, including single edge-triggered flip-flop and double edge-triggered flip-flop. In the new differential flip-flops, a pair of n-channel multiple-input neuron-MOS pull down logic networks is used to replace the nMOS logic tree in the conventional differential flip-flops. The construction of the circuits has been simplified by...
A new enhanced dynamic logic using multiple-input floating-gate MOS(FGMOS) transistors is presented. The circuit technique is designed using an n-channel multiple-input FGMOS pull down logic tree instead of the nMOS logic tree in the conventional enhanced differential cascode voltage switch logic (EDCVSL) circuit. The logic tree of EDCVSL is dramatically simplified by utilizing multiple-input FGMOS...
A novel differential dynamic CMOS logic using multiple-input floating-gate MOS(FGMOS) transistors is proposed. In this circuit family, a pair of n-channel multiple-input FGMOS pull down logic networks is used to replace the nMOS logic tree in the conventional dynamic differential cascode voltage switch logic circuit. A simple synthesis technique of the n-channel multiple-input FGMOS logic tree by...
A novel CMOS quaternary D-type edge-triggered flip-flop using a single latch with neuron-MOS literal circuits is presented. In the proposed circuit, data are sampled into the latch during a short transparency period for rising edge of the clock signal by using the arrow pulse produced by the race-hazard of the clock signal. The quaternary literal functions are realized by using neuron-MOS transistors...
A novel voltage-mode CMOS ternary Schmitt trigger using neuron-MOS transistors is presented. By controlling the voltages of the multiple-input gates, the neuron-MOS literal circuits with hysteresis characteristics are firstly designed. Then, the transmission switches used to pass ternary signal are controlled by the outputs of the literal circuits to realize two hysteresis loops of ternary Schmitt...
A new ternary D flip-flop using one latch is presented. In order to meet the non-transparent demand in flip-flops, the narrow pulses produced by the race-hazard of the clock signal are used to control the latch. In the proposed design scheme, literal functions are realized by using neuron-MOS transistors. Then, the pass transistors used to pass ternary signal are controlled by the outputs of the literal...
A novel Schmitt trigger with controllable hysteresis using neuron-MOS transistors is presented. By selecting the ratio of capacitive coupling coefficients, a Schmitt trigger with different hysteresis characteristics can be achieved. By only varying the external input control signals, the hysteresis window can be conveniently moved without changing its width. The proposed Schmitt trigger has considerable...
A novel circuit realization of two parallel A/D converters based on the Hopfield's neural network is presented. The two neural A/D converters are constructed with comparators and Schmitt triggers, respectively, and they are all designed by using neuron-MOS transistors. The benefit of the proposed circuit realization with neuron-MOS transistors is that the structure of the circuit has been simplified...
In this paper, a new Hamming neural network integrated circuit using neuron-MOS transistor is presented. A matching calculation circuit and a winner-take-all circuit have been designed using neuron-MOS transistor as a key circuit element. The structure of the proposed circuit has been simplified significantly. From the HSPICE simulation results using TSMC 0.35µm double-polysilicon CMOS technology,...
Novel CMOS D-type and modular algebra-based edge-triggered ternary flip-flops using double pass-transistor logic(DPL), are presented. In the proposed circuit scheme, literal functions are also realized by using traditional MOS transistors without any modification of the thresholds. The DPL-based flip-flop has some favourable properties: perfectly symmetrical structure, full logic swing and the maximum...
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