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Hot carrier (HC) reliability of gate-all-around twin Si nanowire field effect transistor (GAA TSNWFET) is reported and discussed with respect to size and shape of nanowire channel, gate length, thickness and kind of gate dielectric in detail. Smaller nanowire channel size, shorter gate length and thinner gate oxide down to 2 nm thickness show worse hot carrier reliability. The worst VD for 10 years...
In this work, fabrication of TSNWFET on SOI with down to 25-nm TiN surrounding gate and 8-nm silicon nanowires is reported with high manufacturability and improved device reliability including reduced junction and gate leakage currents by fully eliminating the bottom parasitic channel existing in previous TSNWFET on bulk Si. And high performance is also obtained to be 1124muA/mum and 1468muA/mum at...
Hot carrier injection (HCI) and negative bias temperature instability (NBTI) reliability of n-channel and p-channel silicon nanowire transistors (SNWTs) have been investigated in this paper. It was found that the worst-case bias for HCI in n-type SNWTs is different from the conventional planar devices, and HCI is not a critical concern for ultra-scaled SNWTs. For the pMOSFETs, NBTI in SNWTs is relatively...
As a part of continued multi-bridge-channel MOSFET (MBCFET) study, we have successfully fabricated 122Mb SRAM cell with 25 nm gate length CMOS MBCFET on bulk Si wafers. The 6-T MBCFET SRAM cell shows high static noise margin (SNM) of 320 mV at Vcc= 0.8 V. Using tall-embedded-gate (TEG) and source/drain (S/D) engineering, 2.6times105 times on/off current ratio and 3.46 mA/mum of on-state current at...
For the first time, we have successfully fabricated gate-all-around twin silicon nanowire transistor (TSNWFET) on bulk Si wafer using self-aligned damascene-gate process. With 10nm diameter nanowire, saturation currents through twin nanowires of 2.64 mA/mum, 1.11 mA/mum for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively. No roll-off of threshold voltages, ~70 mV/dec. of substhreshold...
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