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To meet ever-growing demands for higher mobile data-rates, LTE standards continue to evolve. While carrier aggregation (CA) improves data-rates, it requires wider aggregated signal bandwidth that limits the number of users that can be serviced. Techniques like 256QAM and 4×4 MIMO are attractive because improvements do not need wider signal bandwidth. To support 256QAM and 4×4 MIMO for the 5GHz band,...
The architecture of a frequency synthesizer that generates an arbitrary-frequency output clock from an arbitrary-frequency input clock is presented. This design supports fully-programmable synthesis ratios, including integer-N, fractional-N and rational-K/L ratios. An earlier solution presented by the authors requires an input clock frequency above a few hundred mega-hertz for a low phase noise output...
This paper presents the analysis and implementation of a PLL structure for single-phase grid-connected system. By comparing two different PLL structures based on SRF (synchronous reference frame) and p-q (instantaneous reactive power) theory respectively, a simplified control model of the PLL system is developed. This paper also analyzes the generation of the orthogonal voltage system based on SOGI...
Joint design time and post-silicon optimization for analog circuits has been an open problem in literature because of the complex nature of analog circuit modeling and optimization. In this paper we formulate the co-optimization problem for digitally tuned analog circuits to optimize the parametric yield, subject to power and area constraints. A general optimization framework combing the branch-and-bound...
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