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A 0.9 V 96 muW fully operational low-power digital hearing aid chip is proposed and implemented. An internal status controller is introduced to achieve full operation of the adaptive-SNR analog front end. Dedicated DSP with an additional volume control parameter eliminates any internal overflow and enables the hearing aid to be customized for each individual user. When the input audio band is split...
A low power fully operational digital hearing aid chip, named Clearphone, is proposed and implemented. To achieve both the high energy efficiency and flexibility, it adopts the enhanced adaptive-SNR analog front-end, the dedicated DSP and the heterogeneous Sigma-Delta DAC. Implemented in a 0.18 mum standard CMOS process with a 0.9 V supply voltage, the power consumption of the overall system is only...
An ultra low-power digital signal processor (DSP) is proposed for the digital hearing aid. The DSP has a SNR monitor to vary its internal clock frequency in accordance with the input signal level. Digital filters use hardwired barrel shifters in place of multipliers, and a parameter ROM provides filter parameters. The clock generator consumes only 1 muW at sub-1V. The DSP consumes only 10 muW at 0...
We present radiation data, Total Ionizing Dose and Single Event Effects, on the LSI Logic's commercial 0.18 μm process and its radiation hardened version. Test results, are discussed in this paper. No Single Event Latch-up (SEL) was observed up to a LET of 75 MeVcm2/mg for radiation hardened version, while the commercial process was very sensitive to SEL.
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