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A 13-bit 160MS/s hybrid ADC in 65 nm CMOS is presented in this paper. By combining the pipelined, flash and SAR architectures, a hybrid ADC architecture is proposed to improve the power efficiency. An input offset storage technique of dynamic comparator is proposed to increase the conversion linearity. A reference voltage buffer with the charge compensation is proposed to save power and reduce the...
This paper presents a Flash ADC with low offset dynamic comparators using an offset cancellation technique. By dynamically storing the comparator offset on the input capacitors, the offset is suppressed mostly. Two 5-bit 160MS/s Flash ADCs (Flash-A using the proposed offset cancellation technique and Flash-B without cancellation) are fabricated in 65nm CMOS for comparison. The measure results show...
In this paper, a high speed analog front-end circuit used in a 12bit 1GSps pipeline ADC is presented, the circuit is composed of a high speed on-chip input buffer and a flip-around sample-and-hold (S/H) amplifier, by using N-well Electric potential bootstrapping technique, the circuit acquired a excellent performance at high input frequency. The entire circuit was designed in TSMC 65nm CMOS process...
This paper presents a 14-bit 200MS/s low-power pipelined flash-SAR ADC. A 5-bit front-end without a dedicated sample-and-hold amplifier (SHA) is adopted in the first stage. A 10-bit flash-SAR ADC which is composed of a 3.5-bit flash ADC and a 7-bit asynchronous SAR ADC is used as the second stage, eliminating the need for more pipeline stages. To achieve high performance with power-efficiency, correlated...
This work presents a blind background calibration algorithm for correcting inter-stage gain error and capacitor mismatches in pipelined ADC. Based on the analysis of the density of specific output codes, the algorithm stores the information of the codes and needs only 80 registers. And there is no need to modify the analog circuits, which simplifies the design. Besides, since there is no multiplication...
A power-efficient 14-bit 250MS/s pipelined ADC is presented. With the aid of range-scaling technique, an original single-stage opamp is adopted to replace the conventional large-swing opamp. A novel charge compensation based (CCB) technique effectively reduces input-dependent errors of the reference voltage and it consumes no static current. Total power is reduced further because of opamp sharing,...
Monitoring and evaluation of vascular leakage in brain is important in the research area of brain injuries and edema. A high-resolution photoacoustic microscopy (PAM) was developed to monitor the blood-brain barrier (BBB) permeability using Evans blue (EB) dye. We used a mouse traumatic brain injury (TBI) to validate the usefulness of our system. The uptake of EB in brain vessels was continuously...
This paper presents a 14-bit 200MHz power-efficient pipelined flash-SAR ADC. A 5-bit front-end without a dedicated sample-and-hold amplifier (SHA) is adopted in the first stage. A 10-bit flash-SAR ADC which is composed of a 3.5-bit flash ADC and a 7-bit asynchronous SAR ADC is used as the second stage. To achieve high performance with high power-efficiency in the proposed ADC, correlated level-shifting...
Accurate and robust recognition of burning state for alumina rotary kiln sintering process plays an important role in the design of intelligent control systems. Existing approaches such as image segmentation-based methods could not achieve satisfactory performance. This paper presents a novel multisource data driven-based burning state recognition model to further improve our existing flame image...
In order to improve the recognition performance and avoid the high dimensional feature space by using multi-feature fusion technology, indexes of recognition capability entropy, feature recognition intensity, recognition information entropy, and feature weight are firstly defined. Then, the multi-feature fusion algorithm based on maximal recognition capability entropy and feature selection algorithm...
A low-power 14-bit 150MS/s pipelined ADC is presented. This prototype ADC is fabricated in a 130nm CMOS process with a 1.3-V supply voltage. Range-scaling in the first stage enables a maximal 2Vp-p input signal swing with a power-efficient single-stage opamp. Opamp and capacitor sharing between the first and second stage reduces the opamp power consumption further. And the sample-and-hold amplifier...
This paper reports a low-power transceiver with a reconfigurable sliding-IF (intermediate frequency) architecture used for wireless body area networks hubs covering multiple frequency bands (400, 900 and 2400 MHz). By using this architecture, a 1600–2000 MHz phase-locked-loop (PLL) synthesizer with only 25% tuning range can fully cover these three bands. The multi-band transceiver has been designed...
A digital background calibration algorithm is proposed to overcome nonlinearity caused by finite opamp gain and capacitor mismatch in pipelined analog-to-digital converter (ADC). The scheme, code frequency statistics (CFS), does not modify the classic pipelined stage, needs none of extra testing signals, and reduces the linearity requirement of the analog circuit. CFS is suitable for generic input...
This paper proposes a merged first and second stage for pipelined ADC. It merges the first MDAC and second MDAC by using opamp and capacitor sharing technique to reduce power. For low supply advanced CMOS technology, the range-scaling technique is used to reduce output range in this stage, so the single-stage opamp can be used with low supply voltage to reduce power furthermore. The SHA-less technique...
This paper describes the design and implementation of an information management system of remote stroke rehabilitation based on Internet, including the concept of the system, the composition of the system, implementation of the system, the key technologies of implementation of the system, the functional design of the system, the division of authority for the patients and doctors as well as the process...
Near-infrared spectrum scattered from biological tissue can be used to characterize the optical properties of the tissues. If the optical properties of different parts of vertebra bones are different, a new navigation method in pedicle screw insertion surgery can be proposed. The goal of this study is to develop an optical measurement method which can detect the optical properties of vertebra bones...
Fatigue will be induced when people are watching 3D programs on TV. In order to reduce the negative effect, an experiment was conducted to find how3D film can do harm to the health of people. Electroencephalogram (EEG) and electro-oculogram (EOG) were used as an effective method to measure fatigue. When processing EEG signals, we discovered a new method to get blink signals which can also reflect...
Accurate recognition of burning state is critical in sintering process control of rotary kiln. Recently, flame image-based burning state recognition has received much attention. However, most of the existing methods demand accurate image segmentation, which is quite challenging due to poor image quality caused by smoke and dust inside the kiln. In this study, we develop a more reliable method for...
A new method to get the optical parameters of vertebra bones during pedicle screw insertion surgery was proposed. The method was based on the equation of spatially resolved, steady-state diffuse reflection. The diffuse reflectance was got at the positions of 0.2 cm distance from light source. The measurement system based on light intensity was designed. The light source was 760nm light emitting diode...
This paper established an optimized algorithm for temperature field distribution of rat brain tissue undergoing radio frequency ablation (RFA) treatment. Firstly, adopting the Pennes bio-heat transfer equation, obtained the temperature distribution of rat brain tissue with different RFA temperature and duration by using the finite element analysis software FEMLAB (COMSOL). Then, obtained the optimized...
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