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The parallelism of hardware and the dynamic reconfigurability of FPGAs enable multiple hardware tasks to run concurrently, and also time-share resources by being swapped in and out of the device during runtime. More than ever before, these capabilities are being employed in systems with high-reliability requirements. To improve reliability, a method often used is circuit relocation. However, the static...
The trend in computing is towards the use of FPGAs to improve performance at reduced costs. An indication of this is the adoption of FPGAs for data centre and server application acceleration by notable technological giants like Microsoft, Amazon, and Baidu. The continued protection of Intellectual Properties (IPs) on the FPGA has thus become both more important and challenging. To facilitate IP security,...
The addition of hard blocks such as Block RAMs and Digital Signal Processors, have proven to be good means of improving various performance metrics in FPGAs. This however places stricter constraints on runtime relocation of hardware tasks and hence reduces their application in dealing with permanent faults. In this paper, we present a strategy that enhances the utilization of heterogeneous reconfigurable...
Dynamic partial reconfiguration (DPR) allows runtime access to the configuration memory (CMEM) of FPGAs. A key function that relies on DPR is task reconfiguration, where circuits are multiplexed in time and space in order to reduce device count and cost. Moreover, in mission-critical applications, DPR is used for soft error mitigation (SEM). These two key functions require access to the same CMEM...
As it optimizes the resource utilization of FPGA over time and space, Dynamic Partial Reconfiguration is an important feature of FPGA. The Internal Configuration Access Port (ICAP) controller is an important part of reconfiguration system with which to access the configuration registers of FPGA. By reducing the resources consumed by ICAP controller, more resources will be available for the reconfigurable...
Reconfigurable hardware such as FPGAs offer promising platform for the development of embedded autonomous systems. This is due to their unique combination of high performance and flexibility. However, state-of-the-art FPGAs have large reconfiguration time, which often leads to missed deadlines in real-time systems. They also suffer from considerable fragmentation during runtime placement, leading...
The use of reconfigurable chips such as FPGAs in embedded systems for many runtime applications is limited by large reconfiguration time. Techniques to circumvent this limitation relies on hardware task reuse which preserve certain circuits on the chip. However, the frequent addition and removal of circuits while preserving others on the chip will inevitably lead to fragmentation of its area, in an...
The number of IPs running concurrently on an FPGA has increased in recent years. Communication among these IPs has necessitated the introduction of the network on chip (NoC) for low-power, high-performance, and scalable on-chip networking. While NoCs are superior to traditional shared buses, there is an attendant resource overhead incurred by the NoC links, routers and network adapters. We present...
The ability to relocate hardware tasks in FPGAs is an attractive task management technique, especially in reconfigurable operating systems. A method of relocation involves the modification of the location address of the task while it is being configured. However, the use of encryption to protect bitstreams requires that decryption is done on-chip before relocation. This usually results in a significant...
The image-processing pipeline is the core part of any camera system including digital still cameras, camcorders, camera phones and video surveillance equipments. The image-processing pipeline consists of a number of processing stages that enhance the image or remove any effects that are caused by surrounding conditions. These stages are computationally intensive and need special requirements to meet...
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