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Aiming at improving the detecting probability of weak target and adaptability in multi-clutter background, a new CFAR processing method based on DB4 wavelet (WT-FS-CFAR) is proposed. The proposed method can deal with the wavelet coefficients of the echo signal adaptively and reconstruct a new echo signal. Compared with typical CFAR processor, experimental results show that the proposed method could...
Aiming at achieving high-performance and efficient routing in network-on-chip, a new adaptive STR routing algorithm is proposed based on SRNoC topology in this paper. The proposed routing algorithm can choose the routing paths dynamically and enables the routing hops within 2 between any source nodes and destination nodes. It is mainly made up of router injection port selection and TM output port...
This paper proposes a novel Shared-Resource routing scheme, SRNoC, that not only enhances network transmission performance, but also provides a high efficient load-balance solution for NoC design. The proposed SRNoC scheme expands the NoC design space and provides a novel effective NoC framework. SRNoC scheme mainly consists of the topology and routing algorithm. The proposed topology of SRNoC is...
An application to improve the performance of DDR memory controller based on network processor is described in this paper. The DDR memory controller is designed to prefetch instructions to get the address relationship of consecutive instructions in advance. The controller can be able to utilizing the policy of Open Page or bank interleaving while the current instruction is executing. The performance...
Network-on-Chip has became a mainstream technology to solve the communication problems in Multi Processor SoC (MPSoC); and it has a greatly impact on system's performance, area and power consumption. In order to improve the performance of Network-on-Chip to fulfill the requirements of the MPSoC, this paper presents a dynamic adaptive NoC (DANoC) architecture, which can achieve the topology dynamic...
MQ-encoder is a key bottleneck in the JPEG2000 image compression system. In this paper, a novel architecture for an MQ-encoder with high-throughput is proposed in this paper. The dependence between contexts has been analyzed and extracted. The "start-up" states and remaining states of the index table is separated in this paper. And some measures have been introduced to prevent the pipeline...
Network processor is a type of specific instruction set processor which is used to process the data packet and possess specific circuit. In this paper, based on the testbench of network processor, functional coverage models are built by the two types of functional coverage expression provided by SystemVerilog. The functional coverage can be obtained automatically by these models. According to the...
This paper presents three pause mechanisms of multithreaded processors (micro-engine) of network processor, which is mainly used for dealing with reference instruction. We implement design of RTL-level code, functional simulation and logic synthesis on these three mechanisms. At last according to frequency and hardware resources and the expected performance requirements we select pause method based...
The study in this paper is to solve the compatibility of the PLB and AHB interface. In our FPGA hardware platform, we use the PowerPC embedded in Xilinx Virtex4 as our CPU, which follows the PLB protocol. As our slave IP cores are all designed with the AHB interface, we need to design a PLB-AHB bridge to translate the two protocols. This paper describes in detail the designing of such a bridge, which...
In this paper, we propose a cost-effective way to improve the performance of DRAM based on multi-core system. A novel DRAM controller with instruction prefecthing mechanism is introduced. The controller dynamically selects Open Page(OP) or Close Page(CP) policy by getting some information of future accesses in advance. This DRAM controller with dynamic policy based on instruction prefetching(DP_BIF),...
High performance routers require fast packet buffers to hold packets awaiting transmission[1]. These buffers usually use a memory hierarchy that consist of expensive but fast SRAM and cheap but slow DRAM to meet both, speed and capacity requirements[2]. In this paper, we introduce a particular memory hierarchy as packet buffer architecture which consists of multiple, independent memory channels of...
The study in this paper is aimed at improving the performance of a network processor design (XDNP) based on a Virtex-4 FPGA by using the PlanAhead tool offered by XILINX. PlanAhead gives a unique visibility into the design. The tool can very quickly identify the critical path, and then supply hierarchical floorplanning to achieve faster timing closure. XDNP is targeted at networking applications requiring...
This paper presents an optimized architecture of shared memory controller in packet processing multi-processor system on chip (MPSoC). The rotation priority algorithm in arbitration mechanism is ameliorated so that fairness of the memory access response and continuity of read/write commands are guaranteed. A `ping-pong' structure is adopted in SRAM interface logic which optimizes the memory data throughput...
An integrated SDRAM controller with asynchronous access architecture is proposed. The controller takes charge of data transfer between off-chip SDRAM memory and the multicore multithreaded processors. The interleaving optimization for opposite bank is incorporated into the SDRAM controller, which can reduce memory latency and improve the memory bus performance. FPGA results show that the proposed...
In a memory structure shared by multiple processors based on Multiprocessor Systems on Chip (MPSoC), the efficiency of memory bus access becomes the bottleneck of the overall system efficiency. This paper presents a low-latency SDARM controller structure integrated in MPSoC, which controls the off-chip SDRAM memory. Consecutive same row optimization and odd-even bank optimization are used to eliminate...
A flexible and efficient ECC processor is presented in this paper. We design an application-specific instruction set for the processor. The proposed parallel architecture ECC processor provides the lowest level finite-field operations and supports arbitrary elliptic curves and various ECC algorithms over general prime filed. Based on 130 nm standard-cell technology, the processor requires 184μs for...
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