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This paper presents a new tool flow to realize algorithms in floating-point precision on FPGAs. A customizable multicore soft GPU architecture is used on the hardware side. Two solutions to perform floating-point arithmetic in IEEE-754 single precision are investigated: using standard function calls to GPU-friendly software implementations, or by hardware upgrades to the Processing Elements (PEs)...
This paper explores the capabilities and limitations of soft GPGPU-based computing on fixed-point arithmetic. The work is based on an existing soft GPU architecture which has been improved and extended to cover broader benchmarks. A generic ALU design for modern FPGA architectures is presented. The enhanced ISA includes conditional instructions and global atomic operations. We extended the tool flow...
To handle the stringent performance requirements of future exascale-class applications, High Performance Computing (HPC) systems need ultra-efficient heterogeneous compute nodes. To reduce power and increase performance, such compute nodes will require hardware accelerators with a high degree of specialization. Ideally, dynamic reconfiguration will be an intrinsic feature, so that specific HPC application...
To handle the stringent performance requirements of future exascale-class applications, High Performance Computing (HPC) systems need ultra-efficient heterogeneous compute nodes. To reduce power and increase performance, such compute nodes will require hardware accelerators with a high degree of specialization. Ideally, dynamic reconfiguration will be an intrinsic feature, so that specific HPC application...
The use of reconfigurable FPGA devices to support the execution of computationally intensive software tasks is discussed in this paper. A system architecture consisting of multiple serially-connected FPGAs is developed, where each FPGA holds a pool of reconfigurable regions. An accelerator can be reconfigured into a region, replaced or discarded at runtime. Configurable connection blocks are responsible...
Dynamic and partial reconfiguration is a well-known technique to update the configuration of a field programmable gate array (FPGA) at runtime. Xilinx FPGAs support this feature which enables extensive research in this domain. However, until today the usage and exploitation of partial reconfiguration has a hurdle. The complex development process, as well as the required control at runtime keeps this...
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