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10Gbps Ethernet Security Processor is very important in future network telecommunication. In order to meet the performance of ultra high throughput of 10Gbps ESP, An architecture of multiple SHA-1 IP cores paralleled based crossbar switch are proposed in this paper. Firstly, An ultra high throughput, low power consumption SHA-1 algorithm IP-core are designed, then, an effective scheduling architecture...
Intellectual property (IP) block reuse is becoming the mainstream of system-on-chip (SOC) design. However, the trade of IP blocks poses significant high security risks. Consequently IP protection becomes sensitive and urgent. In this paper, DesignMarker platform used for IP protection is proposed, which is based on watermarking technique. Both netlist-level watermarking module and layout-level watermarking...
How to apply watermarking techniques for IP protection in practice is now the most crucial and urgent problem in the field of IP protection. In this paper, a whole set of design approaches of watermarking systems for IP protection is firstly proposed, including design aim, evaluation indexes, basic framework, and general principles of selecting and designing watermarking models and watermarking algorithms...
In this paper, we introduce a kind of watermarking system for IP protection (IPP). The copyright is encrypted and then embedded into the design as the watermark in buffer insertion stage. This watermarking technique can identify the design copyright uniquely, and is fit for both ASIC using standard cells and full-custom design. We have evaluated the technique on several testing designs, the inserted...
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