The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The societies and their economies, working and living conditions are changing all over the world. That includes the educational systems that are challenged by moving objectives and development targets [6] [10]. Competing businesses and interests at national, regional and international scales are demanding for citizens to acquire and develop much different skills and competences, also new kinds of...
The decade that we have embarked upon presents enormous challenges for Europe. The 2020 strategy for smart, sustainable and inclusive growth recognises the key role higher education must play if the ambitions for Europe in a fast-changing global reality are to be realised [1]. This implies widening access to lifelong learning to as many European citizens as possible and it is vital that measures are...
Symmetric Transparent BIST schemes for RAM modules assure the preservation of the memory contents during periodic testing while at the same time skipping the signature prediction phase required in transparent BIST schemes, achieving considerable reduction in test time. In this work a processor based transparent approach for testing memories is presented. The proposed scheme uses the CPU to perform...
Hardware Trojans are an emerging threat that intrudes in the design and manufacturing cycle of the chips and has gained much attention lately due to the severity of the problems it draws to the chip supply chain. Hardware Typically, hardware Trojans are not detected during the usual manufacturing testing due to the fact that they are activated as an effect of a rare event. A class of published HTs...
In this work an algorithm for embedding test sets containing don't care values into sequences generated by binary counters is utilized and evaluated. Furthermore, a simple, yet effective, technique to decrease test application time is explored. Experiments carried out on ISCAS benchmarks reveal that the proposed scheme results in considerably shorter test sequences.
Input vector monitoring concurrent Built-In Self-Test (BIST) schemes perform testing during the normal operation of the circuit without imposing a need to set the circuit off-line in order to perform the test. In this work we present an input vector monitoring concurrent BIST scheme, specially designed for the testing of ROM modules.
In test set embedding Built-In Self Test (BIST) schemes a pre-computed test set is embedded into the sequence generated by a hardware generator. These schemes have to evaluate the location of each test pattern in the sequence as fast as possible, in order to test as many as possible candidate configurations of the test pattern generator; this problem is known as the test vector-embedding problem....
Transparent BIST schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric Transparent Built-in Self Test (BIST) schemes skip the signature prediction phase required in traditional transparent BIST, achieving considerable reduction in test time. In this work we propose a Symmetric transparent BIST scheme that can be utilized to serially apply march tests...
Input vector monitoring concurrent BIST schemes perform testing concurrently with the operation of the circuit. In this work a novel input vector monitoring concurrent BIST scheme is presented that compares favorably to previously proposed schemes with respect to the required hardware overhead.
Transparent BIST schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric Transparent Built-in Self Test (BIST) schemes skip the signature prediction phase required in traditional transparent BIST, achieving considerable reduction in test time. Previous works on symmetric transparent BIST schemes require that a separate BIST module is utilized for each...
In this paper we present a novel solution to the test vector-embedding problem for sequences generated by accumulators. The time overhead of the solution is of the order O(k), where k is an arbitrarily small constant. Comparisons with previously proposed schemes indicate that the proposed method results in lower test application time.
Due to the widespread adoption and use of handheld mobile devices, the application of mobile technologies in enhancing learning activities has attracted noteworthy research interest. This paper presents an attempt to exploit mobile technologies to simplify the exam management and performance assessment activities of a learning process. The work focuses on key aspects of mobile device and platform...
We present a scheme to reduce the test application time in memory march algorithm application by providing the capability to enable in parallel more than one output of the address decoder during write operations. The reduction in test time, depending on the march algorithm, ranges from 25% to 60%, while the hardware overhead increase for 1 Kbyte SRAM's is less than 2,5%.
Current trends in VLSI designs necessitate low power during both normal system operation and testing activity. Traditional Built-in Self Test (BIST) generators rise the power consumption during testing, necessitating the addition of low-power solutions to the arsenal of BIST pattern generators. In this paper, the utilization of gray codes is investigated as a low-power BIST solution; Experimental...
Memory Built-In Self-Test has become a standard industrial practice. Its quality is mainly determined by its fault detection capability in combination with its required area overhead. Address Generators have a significant contribution to the area overhead. Previously published schemes have proposed the address generator implementations based on counter modules. In this work we present an ALU-based...
In test set embedding Built-In Self Test (BIST) schemes a precomputed test set is embedded into the sequence generated by a hardware generator. These schemes have to evaluate the location of each test pattern in the sequence as fast as possible, in order to test as many as possible candidate configurations of the test pattern generator; this problem is known as the test vector-embedding problem. In...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.