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This paper firstly reports key factors which are to be necessarily considered for the successful two-bit (four-level) cell operation in a phase-change random access memory (PRAM). They are: 1) the write-and-verify (WAV) writing of four-level resistance states; and 2) the moderate-quenched (MQ) writing of intermediate resistance levels, 3) the optimization of temporal resistance increase (so-called...
We have successfully demonstrated a world smallest 0.25 μm2 cell ITIC 64 Mb FRAM at a 130 nm technology node. This small cell size was achieved by scaling down a capacitor stack, using the following technologies: a robust glue layer onto the bottom electrode of a cell capacitor; 2-D MOCVD PZT technology, novel capacitor-etching technology; and a top-electrode-contact-free (TEC-free) scheme. The new...
We discuss key technologies of 180 nm-node ferroelectric memories, whose process integration is becoming extremely complex when device dimension shrinks into a nano-scale. This is because process technology in ferroelectric integration does not extend to conventional shrink technology due to many difficulties of coping with MIM (metal-insulator-metal) capacitors. The key integration technologies in...
In order to realize a cost-effective high density FRAM product over 64-Mb, it is inevitable to develop technologies for a small cell and large wafer size without degradation during full integration. We have successfully demonstrated a fully functional 0.16 mum2 capacitor size, 64-Mb, 1T1C FRAM on an 8-inch wafer by introducing new integration technologies at 150 nm technology node. One of the key...
64 Mb FRAM with a 1T1C scheme has progressed greatly for mass production in terms of a highly reliable device. For the first time, package-level reliabilities of the memory were evaluated systematically and massively. The authors scrutinized the device reliabilities in accelerated manners, one of which is high-temperature-operating-life (HTOL) test; and the other is high-temperature-storage (HTS)...
Fully functional 512Mb PRAM with 0.047mum2 (5.8F2) cell size was successfully fabricated using 90nm diode technology in which the authors developed novel process schemes such as vertical diode as cell switch, self-aligned bottom electrode contact scheme, and line-type Ge2Sb2Te5. The 512Mb PRAM showed excellent electrical properties of sufficiently large on-current and stable phase transition behavior...
Advanced ring type technology and encapsulating scheme were developed to fabricate highly manufacturable and reliable 256Mb PRAM. Very uniform BEC area was prepared by the advanced ring type technology in which core dielectrics were optimized for cell contact CMP process. In addition, relatively high set resistance was stabilized from encapsulating Ge2Sb2Te5 (GST) stack with blocking layers, thus...
We have successfully demonstrated a 0.34mum2 COB cell 1T1C 64Mb FRAM at 150nm technology node. The minimum signal window between data "1" and data "0" of 64M bit cells was evaluated to 300mV at 85degC, 1.6V VDD. This wide signal window was achieved by introducing advanced anneal technology and optimized capacitor layout, from which the variation of individual cell charge was greatly...
We have made great progress for mass production of a highly reliable 1.6V, 0.18 mum 1T1C FRAM embedded smart card. For mass production, our device has to pass standard qualification tests on the package level. These contain the infant life test (ILT), the high temperature operating life (HTOL), the endurance and the high temperature storage (HTS) test. Problems in the PZT capacitor integration scheme...
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