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Nowadays FFT convolution is widely applied to digital signal processing (DSP), and the past few years have witnessed the development of the heterogeneous multicore programmable system (HMPS). In addition, HMPS has been the mainstream in the field of DSP. So it is very important to study the high efficient implementation of large FFT convolution on the HMPS. In this paper, a high efficient pipelined...
In the modern digital signal processing, matrix multiplication is the most typical and basic computing as well as the most important type of test set in the processor performance evaluation benchmarks. Optimizing hardware architectures and algorithm mapping strategies are two common methods to improve the efficiency of matrix multiplication on multi-core systems. When the hardware architecture is...
Packet Connect Circuit protocol is one of the NoC communication methods. Follow the PCC protocol, the data is transmitted in form of circuit through the route established by packet switching. However, there exists disadvantage in the traditional SPCC (single path Packet Connected Circuit, SPCC) routing algorithm whose rate of channel building will slow down when the chip is congest, resulting in the...
Firstly, this paper introduces the classification of different abstraction level of system model and puts forward these questions needed to be solved during the establishment of system model. Secondly, it gives the analysis of the advantages and disadvantages of all existing solutions and implements the modeling based on the method of interface encapsulation. Thirdly, the paper elaborates the merits...
Often graphic processing units (GPGPUs) are used for data processing as the range-Doppler algorithm is computationally expensive and highly parallel. However, GPGPUs may not be an appropriate solution for applications with strictly constrained space and power requirements. In this paper, we implemented a FPGA-based multi-core system for SAR data processing with Range-Doppler algorithm. Our system...
The decomposition of signal subspace and noise subspace is a difficult problem for hardware implementation of MUSIC algorithm. In order to solve the above problem, this paper researches multiple Jacobi algorithms and adopts the combination of the sorted and clearance Jacobi algorithm to improve the efficiency. Meanwhile, this paper gives some algebra for source number estimation. Compared with traditional...
In the MUSIC algorithm, as the final space signal search module, the spectrum peak search plays a vital role in the design. It is quite complicated, because of the choice of search methods, as well as to determine the scope of the search. To solve this problem, we use a two-step search method to determine the final orientation of spatial signal. This paper has completed a spectrum peak search module...
Compared with general Single-core systems, Multi-core systems not only have higher computing capabilities and lower power consumption but also bring high-throughput and high-parallel challenges to the communication on the chip. Depending on the design of traditional 2D-mesh Network on Chip (NoC), this paper researches a Dual-port NoC (DPN), which further enhances the parallelism of multi-core systems,...
Firstly, FFT is widely applied to digital signal processing, and secondly, the past few years have witnessed the development of multi-core systems, which have been the mainstream. So it is important to study the high efficient implementation of large FFT on the multi-core systems. This paper presents one implementation of large FFT on homogeneous multi-core system and achieves a good balance between...
In Multi-processor Systems on Chip (MPSoC), data interacts frequently between processors and off-chip memory. Higher bandwidth utilization of memory interface (MI) is needed urgently by parallel multi-tasks in MPSoC. Referring to the multi-process time-shared scheduling algorithm of CPU, this paper discusses a parallel multi-access technique on user side which applies to MPSoC. This technique utilizes...
3D NoC has the advantages of low communication delay, low power consumption and high data throughput, but, at the same time, suffers from heat dissipation problem. We propose the concept of temperature gradient as the basis for 3D NoCs routing. By monitoring the temperature of every node, the run-time temperature management (RTM) can calculate the temperature gradient map, and the routing decision...
To solve the congestion of NoC caused by overload such as injection rate increase, this paper proposes a novel routing algorithm, that is Dynamic and Mixed Routing(MIXROUT) which is based on XY Routing(XY) and Multiple and Load-Balance Path Routing(MULTI). Although MULTI is an adaptive routing that can relieve traffic congestion state, it has a higher operating power and temperature than other routing...
H.264/AVC has excellent compression efficiency and network-friendly design, but it gets the advanced performance at the expense of highly complex calculation, resulting in huge hardware cost, especially motion estimation (ME) module. To reduce the logic resource consumption (LRC) without any obvious increase of the bit-rate, this paper simplifies the calculation of the block matching parameter with...
Packet-circuit switching adopted by network on chip is a new data transmission protocol, which establishes a route by sending a request packet and transfers data by circuit switching. In order to make the network based on the protocol show excellent performance, we build data transmission link as rapidly and successfully as possible, which depends on the quality of routing algorithm. In this paper,...
Three dimensional network-on-chip (3D NoC) is motivated to achieve better performance, functionality, and packaging density compared to 2D NoC. To facilitate performance evaluation for the design stage, an accurate and flexible environment for simulating the 3D NoC performance is necessary. In this paper, we present a complete high-level simulation platform for 3D NoC called Meshim, based on SystemC,...
New tendencies envisage multi-core as a promising solution for embedded application. And the key challenge is how to improve the communication efficiency. In this paper, we propose improved on-chip communication architecture for multi-core embedded system The presented on-chip communication protocol is based on packet connected circuit (PCC), but we improve it to fit different frequency requirements...
Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for multi-core System on Chip, of which there are three kind of components, processing element(processor, memory, IP, etc), communication element(such as router) and interface module between router and PE. One of the key problems is how to solve the memory bottleneck under the circumstances that multiple...
Unlike traditional SoC (System-on-chip) chip, multiprocessor chip that contains multiple independent processors, each processor owns different applications, so we need to make a reasonable multiprocessor chip initialization program. This paper proposes a design for the multiprocessor system initialization. The main contribution is as follows: Firstly, one method for the implementation of multiprocessor...
Wireless video interphone cannot only provide portability, but also connect people through video communication, so it gains more and more interest in consumer electronics. To design such systems, it needs high performance video processing engine. In this paper, a Multi-processor system on a chip (MPSoC) is designed, in which there are one 32-bit RISC CPU and a low power, high performance H.264 codec...
Inter-Processor communication synchronization in multi-processor system-on-chip (MPSoC) is one of the key factors for the whole chip performance. It cannot only affect the efficiency of task-level parallelism, but also has high dependency on MPSoC hardware architecture. Two synchronization mechanisms, i.e. mailbox and packet switching, are studied and analyzed in Network on chip based MPSoC. At first,...
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