In the modern digital signal processing, matrix multiplication is the most typical and basic computing as well as the most important type of test set in the processor performance evaluation benchmarks. Optimizing hardware architectures and algorithm mapping strategies are two common methods to improve the efficiency of matrix multiplication on multi-core systems. When the hardware architecture is determined, it is increasingly important to improve mapping technology. In this paper, with the parallelism, speedup and task time as evaluation indexes, the on-chip memory and communication bandwidth as constraints, the influence of different mapping strategies for matrix multiplication on the heterogeneous multi-core system interconnected by NoC (Network on chip) is researched. The above results have certain reference significance not only for the evaluation technology but also for improving the performance and the selection of hardware architectures of the heterogeneous multi-core system.