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3D ICs can take advantage of a scalable communication platform, commonly referred to as the Networks-on-Chip (NoC). In the basic form of 3D-NoC, all routers are vertically connected. Partially connected 3D-NoC has emerged because of physical limitations of using vertical links. Routing is of great importance in such partially connected architectures. A high-performance, fault-tolerant and adaptive...
3D-NoC has emerged to provide fast and power efficient connection between the layers of 2D-NoCs using Through-Silicon-Vias (TSV). Thermal stress, warpage, impurities and misalignment during the manufacturing process make these expensive TSVs vulnerable to faults. Chips with faulty TSVs should be either discarded or utilized by providing a proper fault-tolerant method. In this paper, we target designing...
The cost and reliability issues of TSVs move 3D-NoCs toward heterogonous designs with limited number of TSVs. However, designing a deadlock-free routing algorithm for such heterogonous architectures is extremely challenging due to the increased possibilities of forming cycles between and within layers for 3D designs. In this paper, we target designing a routing algorithm for heterogeneous 3D-NoCs...
This paper suggests a mechanism to increase the fault tolerance of switches which are used in the reconfigurable network-on-chip. The focused reconfigurable network-on-chip is composed of some simple switches having been inserted between adjacent routers in the mesh topology in order to increase the performance. In other words, the routers which communicate the most are connected to each other directly...
In this paper, First an analysis of the effects of transient faults using simulation-based fault injection is presented in System-on-Chip Wire (SoCWire) and then a fault-tolerant infrastructure is mentioned and results is reported. Different fault models such as dead clause, stuck then, micro-operation, crosstalk, dead process and SET (Single Event Transient) have been used to evaluate the transient...
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