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The continuous transistor scaling and extremely lower power constraints in modern VLSI chips can potentially supersede the benefits of the technology shrinking due to reliability issues. Due to external aggression factors, e.g., radiation and temperature gradients, the CMOS devices flawless functioning cannot be guaranteed any more. Thus, design time Integrated Circuits (ICs) reliability assessment...
A novel fault tolerant methodology known as Codeword Prediction Encoder (CPE) for reliable data transmission using unreliable hardware is proposed. Simulation results show that performance of CPE is much better as compared to transmitting data by employing traditional encoding methodology. It is shown that by employing Min-sum decoding mechanisms and a strong encoder r = 1/2 and dv = 4, it is possible...
Aggressive technology scaling and ultra low power constraints have resulted in less predictable device behavior complicating timing analysis/estimation. The traditional delay models fail to accurately capture the circuit behavior under such conditions. This paper proposes a novel highly accurate Inverse Gaussian Distribution (IGD) based delay model applicable to both combinational and sequential elements...
Traditional logic synthesis methodologies are driven by timing, power, and area constraints. However, due to aggressive technology shrinking and lower power requirements, circuit reliability is fast turning out to be yet another major constraint in the VLSI design flow. Soft errors, which traditionally affected only the memories, are now also resulting in logic circuit reliability degradation. In...
The low reliability of advanced CMOS devices has become a critical issue that has to be considered in the digital IC design flow. This paper introduces a design time methodology to address and improve the reliability of combinational circuits. The key idea is to employ local transformation rules, a methodology that were extensively used for area, delay, and power optimizations and demonstrate that...
With the advent of deep submicron CMOS technology, process parameter statistical variations are increasing resulting in unpredictable device behaviour. The issue is even aggravated by low power requirements which are stretching transistor operation into near/sub threshold regime. Consequently, traditional delay models fail to accurately capture the circuit behaviour. In view of this we introduce an...
The low reliability of advanced CMOS devices has become a critical issue that can potentially supersede the benefits of the technology shrinking process. This is making the design time reliability assessment and optimization a mandatory step in the IC design flow. As part of our ongoing research, we describe an algorithm based on probability analysis and logic principles for computing the impact of...
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