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We report a record-setting low NMOS contact resistivity of 1.2×10−9 Ωcm2 compatible with Ti/Si system and dopant segregation Schottky (DSS) based solution. The ultra-low contact resistivity of Ti/Si system is demonstrated with Highly Doped Si:P Epi layer and P implantation using conformal plasma implant followed by millisecond laser anneal. Additionally, we show that short-pulse nanosecond laser as...
We report a PMOS contact resistivity (pc) improvement strategy by forming Ge-rich contact interface which is compatible to Ti/Si(Ge) system and CMOS integration flow. Short pulsed (nsec) laser anneal and advanced treatment during pre-clean have shown to be effective to segregate Ge towards SiGe surface resulting in PMOS ρc improvement. With Ge% increasing from 45 to 100%, pc improved three-fold, from...
We report a record setting low NMOS contact Rc of 2e−9 Ωcm2 with an all-silicon based solution. The ultra-low contact resistivity of Ti/Si system of 2e−9 Ωcm2 has been demonstrated with Highly Doped Si:P (HD Si:P) EPI layer which is compatible with FinFET S/D structures combined with millisecond laser anneal activation (DSA). Additionally, we show the pathway to further improve contact resistivity...
Low specific contact resistivity (7E-9 Ohm.cm2) was achieved for contacts with TiSix to in-situ epitaxially doped Si:P n-SD regions by use of Se implantation prior to Ti deposition. The key to this achievement is the optimization of implant energy and dose, and use of millisecond laser anneal to heal the implant damage, while allowing sufficient inter-mixing of Ti, Si, Se and P atoms across a smooth...
Contact resistivity (ρC) reduction for n-SD (source/drain) with Se+ implant was evaluated for different integration schemes. It is found that Se+ implant energy is one of the most critical process parameters for ρC improvement, achieved by placing the Se+ peak close to silicide (TiSi2 or NiPtSi)/Si interface and minimized implant damage. Recovery of implant damage to silicide and n-SD region was achieved...
The continuing reduction of contact resistivity (ρC) is a critical challenge for device performance. In this paper the ρC reduction for n-SD (source/drain) is demonstrated using post-silicide implantation of Se or P into Ni(Pt) silicide, with various energies/doses and laser anneal conditions. The improvement of ρC is achieved without sacrificing junction integrity/leakage. Hence laser assisted post-silicide...
Gate-first (GF) high-k metal gate (HKMG) for LSTP/LOP logic and DRAM periphery applications requires an efficient and low-cost effective work function (eWF) solution. We demonstrated TiAlN for pFET eWF tuning without appreciable EOT, Jg, and interface degradation. Hence TiAlN is shown to be a key enabler to realize process-friendly and cost-effective GF HKMG implementation.
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