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Error tolerance techniques are widely used to protect processor pipelines from variation induced timing errors. In this paper, we propose two standard cell library tuning techniques to optimize error tolerant processor pipelines for power and area savings. The design utilizes positive slack available in the pipeline stages and re-distributes it to the preceding error-prone critical paths using slack...
Process, voltage and temperature variations are on the rise with technology scaling. Nano-scale technology requires huge design margins to ensure reliable operation. Worst case design margining consumes significant amount of circuits and systems resources. In-situ error detection or correction is an alternative method for cost effective variation tolerance. However, existing in-situ error detection...
There is much focus on timing error resilience for the speed critical paths of processors. In the context of growing parameter variations with technology scaling and voltage scaling, resilience helps to ensure functional correctness. Moreover it allows the chip to stretch its operating voltage and frequency beyond the conventional limits to meet the demand for high performance and low power. Conventionally,...
In this paper, an innovative design of a miniaturized heterogeneous 3DIC-based wireless sensor node (WSN) is proposed. The design contains stacks of radio frequency (RF) die, mixed-signal die, digital die, and integrated antenna die using the through silicon via (TSV) technology. Significant enhancements to the existing 2D design and verification flow are developed to solve the critical concerns of...
3DIC's, the flagship for the “More than Moore Law” movement are already an integral part of the Semiconductor and Manufacturing industry and lot of investigations are going on within different sectors of the industry to efficiently fabricate 3DIC's. If you peep deep into the design process, everyone is trying to make it upward compatible with the 2D design for effective reusability. The methodology...
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