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A delay‐locked loop (DLL) based clock and data recovery (CDR) circuit with a half‐rate clock is proposed. The CDR includes a coarse and a fine tuned block, in which the novel coarse and fine phase detectors form closed loops. It is designed in a 65‐nm complementary metal‐oxide semiconductor (CMOS) process using a 1.2‐V supply voltage. The simulation results show that it can cover a wide operating...
A wide operating range and fast locking delay-locked loop (DLL) based frequency quadrupler that includes an eight-phase-clock generator and an edge combiner is proposed. The eight-phase-clock generator is composed of a coarse-code generator, a fine-code generator and a digital controlled delay line, which uses four differential delay units to generate equally spaced eight-phase clocks. The coarse-code...
This paper proposes a new 16-bit adder which has a wide operating voltage range and higher energy efficiency for near-threshold voltage operation. This adder employs the architecture of carry look ahead (CLA) and gates of sense-amplifier based pass-transistor logic (SAPTL). Three other designs applying the same architecture and traditional logic gates (that is, double pass-transistor logic (DPL) gates...
In this paper, a 1.25 Gpbs all-digital burst-mode clock and data recovery (BM-CDR) circuit with embedded time-to-digital converter (TDC) is presented. The proposed BM-CDR circuit uses an amendatory calculation method to achieve less quantization error. Current-starved inverters with control signals are used to realize fine-TDC to improve the resolution and reduce the power. This circuit is implemented...
A wide range delay-locked loop (DLL) based clock and data recovery (CDR) circuit including coarse and fine tune blocks is proposed in this paper. The coarse tune block adopts a time to digital converter and digital control delay line to widen the frequency capture range, reduce locking time and prevent the false locking problem. In the fine tune block, a novel phase detector combines the tasks of...
This paper presents a clock and data recovery (CDR) delay locked loop that operates in high frequency while keeping low jitter performance. The data rate can be twice the reference clock frequency. A self-starting-control circuit widens the phase capture range. In order to compensate for the attenuation of channel, an equalizer comprised of two peaking amplifiers is employed in front end of CDR. The...
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