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In this study, various fault tolerant techniques have been handled for pipelined MIPS-32 microprocessor in order for correct operation in the presence of faults and reliability analysis have been performed. For this purpose, register file is focussed on due to the fact that it is one of the most important unit of microprocessor. Register files designed with the fault tolerant methods have been synthesized...
This paper represents a new method to protect register file of a RISC microprocessor against MBUs. The key idea is combining the most important properties of two methods in the literature. One of them is a type of information redundancy called as matrix code that has detection and correction capability. The other one is TMR which is a widely used hardware redundancy technique and masks faults. The...
The Universal Verification Methodology is a standard which is designed to enable creation of reusable, robust and interoperable verification IP and testbench components. In this work, we implemented layered UVM testbench for SpaceWire which is a spacecraft communication network based in part on the IEEE 1355 standard of communications. This design helps further analyzes of SpaceWire by testing different...
In order to implement reliable digital system, it is becoming important making tests and finding bugs by setting up a verification environment. It is possible to set up effective verification environment by using Universal Verification Methodology which is standardized and used in worldwide chip industry. In this work, the slave circuit of Serial Peripheral Interface, which is commonly used for communication...
Embedded microprocessors are widely used in most of the safety critical digital system applications. A fault in a single bit in the microprocessors may cause soft errors. It has different affects on the program outcome whether the fault changes a situation in the application. In order to analyse the behaviour of the applications under the faulty conditions we have designed a custom verification system...
In this paper, a throughput enhanced version of a new True Random Bit Generator (TRBG) based on a time-delay sampled-data system is proposed. This new TRBG has both analog and digital parts, which provides the dynamic behavior and the sample and delay process, respectively. The simple system equations and the ease of implementation make this new TRBG very practical. The only required components for...
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